EEL6323-S10-HLec07-MultiStageLE-P2-4spp

I like 4 10 12 14 16 10 20 05 14 07 n n 115 126 151

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– I like = 4 1.0 1.2 1.4 1.6 1.0 2.0 0.5 1.4 0.7 N / N 1.15 1.26 1.51 ( =2.4) ( =6) D(N) / 0.0 Example: extracting logical effort from datasheets INVX1 Determine p, g and for INVX1 from datasheet – Unit inverter capacitance is • 3.6fF – Parasitic or intrinsic delay is • (25.3+14.6)/2=20ps – Slope of delay vs. load capacitance is the average of rising and falling K load values • (4.53+2.37)/2 ns/pF Elec tr ic al Ef f or t: h = C out / C in Normalized Delay: d Inverter 2-input NAND g = 1 p = 1 d = h + 1 g = 4/3 p = 2 d = (4/3)h + 2 Ef f ort Delay: f Parasitic Delay: p 012345 0 1 2 3 4 5 6 Recall d abs = (gh+p) τ τ t pd = 20ps + (3.6fF/gate)(h gates)[(4.53+2.37)/2 ns/pF] = (20ps + 12.4h) ps = tau (20ps/tau + (12.4/tau)h) g=1=12.4/tau tau=12.4 p inv = 20ps/12.4ps = 1.61 d=(gh+p)=(h+1.61)
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3 NAND2 Determine p, g and for NAND2X1 from datasheet – Unit NAND2X1 capacitance is • 4.2fF – Parasitic or intrinsic delay is • (31.3+19.5)/2 – Slope of delay vs. load capacitance is the average of rising and falling K load values • (4.53+2.84)/2 ns/pF Elec tr ic al Effort: h = C out / C in Normalized Delay: d Inverter 2-input NAND g = 1 p = 1 d = h + 1 g = 4/3 p = 2 d = (4/3)h + 2 Effort Delay: f Parasitic Delay: p 012345 0 1 2 3 4 5 6 Recall d abs = (gh+p) τ τ t pd = (31.3+19.5)/2 + (4.2fF/gate)(h gates)[(4.53+2.84)/2 ns/pF] = (25.4ps + 15.5h) ps g=15.5/tau=1.25=5/4 p inv = 25.4ps/12.4ps = 2.05 Example Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3:0] – Each input may drive 10 unit-sized transistors Ben needs to decide: – How many stages to use? – How large should each gate be?
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