32 Asynchronous Circuit Design Asynchronous circuits do not rely on globally

32 asynchronous circuit design asynchronous circuits

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3.2. Asynchronous Circuit Design Asynchronous circuits do not rely on globally periodic timing signals (clocks), but they need to operate under additional design constraints. All asynchronous circuits must be glitch-free (under a certain timing model), which often results in additional logic. Asynchronous circuits also require explicit handshake signals between circuit blocks. While requiring additional overhead, handshak- ing does make it easy to connect circuit blocks together because timing and data requirements are communicated explicitly. As operating considerations change (tempera- ture, V dd , variations in manufacturing), providing explicit timing information allows the system to respond to changes in delay of the critical path. Because a clock sig- nal is not driven while the processor is idle, asynchronous circuits provide a native way of reducing energy from cir- cuit switching for low duty cycle applications. One common class of asynchronous circuits are quasi- delay-insensitive (QDI) circuits that are insensitive to delays in gates and wires but require isochronic forks. An isochronic fork is a forked wire where all branches have exactly the same delay. 3 QDI circuits are used widely in the asynchronous design community to build full micro- processors. Synthesis techniques are available for QDI circuits. 3.3. VDD-Gating Gating the power supply has been used as a circuit tech- nique to reduce the subthreshold leakage current con- sumed in a system. 18 In this work, the authors show how VDD-gating can reduce leakage current by roughly 98% with an additional area cost of 3% and little performance penalty. The downside of this technique is the loss of cir- cuit state once the block has been cut-off from the power supply. Therefore, microarchitecture support is required to efficiency manage gating transistors based on application needs. 4. HARDWARE FOR WIRELESS SENSOR NETWORKS Recently proposed systems for wireless sensor net- works utilize different circuit techniques and architecture approaches. In this section we describe several categories of hardware designs for WSN and reference prototypes for each category. First we categorized systems based on the circuit tech- niques employed to reduce total energy consumption. Subthreshold operation —By using a power supply less than the threshold voltage, systems such as the Subliminal processor from the University of Michigan are able to trade off performance for reduced active power consumption. Asynchronous Circuits —Processors such as SNAP from Cornell University eliminate clock power by relying on asynchronous circuits. Power Supply Gating —To address increasing leakage current, systems from Harvard University and the Univer- sity of California employ transistors that switch the power supplies of unused blocks. Each of these systems take differing approaches to architecture support for applications.
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  • Fall '18
  • Mr. Bhullar
  • Sensor node, Wireless sensor network

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