00 Level 0 01 Level 1 10 Level 2 11 Level 3 2972 CMP Control Register 1 CMP x

00 level 0 01 level 1 10 level 2 11 level 3 2972 cmp

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00 Level 0 01 Level 1 10 Level 2 11 Level 3 29.7.2 CMP Control Register 1 (CMP x _CR1) Address: 4007_3000h base + 1h offset = 4007_3001h Bit 7 6 5 4 3 2 1 0 Read SE WE TRIGM PMODE INV COS OPE EN Write Reset 0 0 0 0 0 0 0 0 CMP x _CR1 field descriptions Field Description 7 SE Sample Enable At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time. 0 Sampling mode is not selected. 1 Sampling mode is selected. 6 WE Windowing Enable At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time. 0 Windowing mode is not selected. 1 Windowing mode is selected. 5 TRIGM Trigger Mode Enable CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled. Table continues on the next page... Chapter 29 Comparator (CMP) KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc. 515
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CMP x _CR1 field descriptions (continued) Field Description CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC in order to generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received. See the chip configuration chapter for details about the external timer resource. 0 Trigger mode is disabled. 1 Trigger mode is enabled. 4 PMODE Power Mode Select See the electrical specifications table in the device Data Sheet for details. 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. 3 INV Comparator INVERT Allows selection of the polarity of the analog comparator function. It is also driven to the COUT output, on both the device pin and as SCR[COUT], when OPE=0. 0 Does not invert the comparator output. 1 Inverts the comparator output. 2 COS Comparator Output Select 0 Set the filtered comparator output (CMPO) to equal COUT. 1 Set the unfiltered comparator output (CMPO) to equal COUTA. 1 OPE Comparator Output Pin Enable 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. 0 EN Comparator Module Enable Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and consumes no power. When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. 0
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  • Spring '08
  • M.SHANBLATT
  • Microprocessor, Central processing unit, ........., Status register, Direct memory access, Freescale Semiconductor, Inc

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