16 cout cin sum150 a150 b150 a30 sum30 cout Add4 Add4 Add4 Add4 b30

16 cout cin sum150 a150 b150 a30 sum30 cout add4 add4

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Add_16 16 16 16 c_out c_in sum[15:0] a[15:0] b[15:0] a[3:0] sum[3:0] c_out Add_4 Add_4 Add_4 Add_4 b[3:0] a[7:4] b[7:4] a[11:8] b[11:8] a[15:12] b[15:12] 4 4 4 4 4 4 4 4 sum[7:4] sum[11:8] sum[15:12] c_in c_in4 c_in8 c_in12 M1 M2 M3 M4 Add_16 Chapter 2: Verilog HDL - Models and Synthesis 20 module Add_16 (sum, c_out, a, b, c_in); output [15:0] sum; output c_out; input [15:0] a,b; input c_in; wire c_in4,c_in8,c_in12,c_out; Add_4 M1 (sum[3:0],c_in4,a[3:0],b[3:0],c_in); Add_4 M2 (sum[7:4],c_in8,a[7:4],b[7:4],c_in4); Add_4 M3 (sum[11:8],c_in12,a[11:8],b[11:8],c_in8); Add_4 M4 (sum[15:12],c_out,a[15:12],b[15:12],c_in12); endmodule b c_out a sum Add_half b c_out sum a Add_half c_in Add_full Add_half
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