6. (5) Which of the following best describes the circuit below? ABQ(t+1)00Q(t)01110011??? 4
a.D Latchb.D Flip-flopc.S-R Latchd.S-R Flip-flope.ComparatorThis is a latch since a change in the output is not coincident with a clock edge. The output is set to 1 whenever input1 goes from 0 to 1. The output is cleared to 0 whenever input2 changes from 0 to 1. As long as input1 and input2 are both 0, the output retains its state. Therefore, this is an S-R Latch . 7. Recall that performing a read from a dynamic RAM (DRAM) requires that the chip precharge before it can supply the requested data. Assume that the precharge takes 6ns and, once precharged,it takes 10ns to output the requested data in response to a read operation or to store the input data for a write operation. Also recall that our MIPS pipeline system employs a Harvard Architecture, transfers 32 bits at a time between the CPU and memory, and each pipeline stage consumes one clock cycle. a)(5) What is the maximum clock rate (expressed in GHz) that can be used for our 5-stage pipelined system if this type of DRAM is used for the memory? . b)(5) If the instruction memoryis implemented as a single memory module with a storage capacity of 220bytes, what is its width and its depth? . . 8. Suppose that our MIPS pipelined processor has a clock rate of 80 MHz and uses an instruction memory consisting of 2 memory modules. Each memory module is 16 bits wide and has a depth of 65536 (216). What is the maximum cycle time (in nano-seconds) for the instruction memory if there are no pipeline stalls and the instruction memory is:a (5) Low-order interleaved? 5
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- Fall '09