MAxloads loadnumber MEMorysize sizeinKB SCAnmemorysize sizeinKB SAmple integer

Maxloads loadnumber memorysize sizeinkb

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] [-MAxloadsload_number][-MEMory_sizesize_in_KB] [-SCAn_memory_sizesize_in_KB][-SAmple [integer]] [-IDDQ_file] [-DEBug [-Libwork_dir]][-MODE_Internal | -MODE_External]
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Generating Test PatternsCreating an IDDQ Test SetScan and ATPG Process Guide, V8.2008_3225August 2008For FlexTest:SAVe PAtternsfilename[format_switch] [-EXternal] [-CHain_test | -CYcle_test | -ALl_test][-BEginbegin_number] [-ENDend_number][-CEll_placement {Bottom | Top | None}] [proc_filename -PROcfile][-PAttern_sizeinteger] [-Serial | -Parallel] [-Noz][-NOInitialization] [-NOPadding | -PAD0 | -PAD1] [-Replace] [-One_setup]You save patterns to a filename using one of the following format switches:-Ascii, -BInary, -Fjtdl, -MItdl, -STil, -CTL, -TItdl, -Wgl, -TSTl2, or -Verilog. For informationon the remaining command options, refer to theSave Patterns in theATPG and FailureDiagnosis Tools Reference Manual.For more information on the test data formats, refer to“Saving Timing Patterns” on page 324.Creating an IDDQ Test SetFastScan and FlexTest support the pseudo stuck-at fault model for IDDQ testing. This faultmodel allows detection of most of the common defects in CMOS circuits (such as resistiveshorts) without costly transistor level modeling.“IDDQ Test” on page 38 introduces IDDQtesting.Additionally, FastScan and FlexTest support both selective and supplemental IDDQ testgeneration. The tool creates a selective IDDQ test set when it selects a set of IDDQ patternsfrom a pre-existing set of patterns originally generated for some purpose other than IDDQ test.The tool creates a supplemental IDDQ test set when it generates an original set of IDDQpatterns based on the pseudo stuck-at fault model. Before running either the supplemental orselective IDDQ process, you must first set the fault type to IDDQ with theSet Fault Typecommand.During selective or supplemental IDDQ test generation, the tool classifies faults at the inputs ofsequential devices such as scan cells or non-scan cells asBlocked (BL) faults. This is becausethe diversity of flip-flop and latch implementations means the pseudo stuck-at fault modelcannot reliably guide ATPG to create a good IDDQ test. In contrast, a simple combinationallogic gate has one common, fully complementary implementation (a NAND gate, for example,has two parallel pFETs between its output and Vdd and two series nFETs between its output andVss), so the tool can more reliably declare pseudo stuck-at faults as detected. The switch levelimplementation of a flip-flop varies so greatly that assuming a particular implementation ishighly suspect. The tool therefore takes a pessimistic view and reports coverage lower than itactually is, because it is unlikely such defects will go undetected for all IDDQ patterns.Using FastScan and FlexTest, you can either select or generate IDDQ patterns using severaluser-specified checks. These checks can help ensure that the IDDQ test vectors do not increaseIDDQ in the good circuit. The following subsections describe IDDQ pattern selection, testgeneration, and user-specified checks in more detail.
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Scan and ATPG Process Guide, V8.2008_3
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