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Suppose that the adder substractor circuit has been

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Suppose that the adder-substractor circuit has been designed for twos-complement numbers. It computes the sum Z = X + Y when control line SUB = 0 and the difference Z = X – Y when SUB = 1. An overflow flag v is to be added to the circuit, but it is not possible to access internal lines. In other words, only those data and control lines can be used to compute v. Construct a suitable logic circuit for v. (15-marks) 16. Consider the adder-substractor , assuming that it has been designed for sign- magnitude numbers. It computes the sum Z = X + Y when control line SUB = 0 and the difference Z = X – Y when SUB = 1. Assume that the circuit contains an n-bit ripple-carry adder and a similar n-bit ripple-borrow substractor and that you have access to all internal lines. Derive a logic equation that defines an overflow flag v for this circuit. (10-marks) 17. Show how to extend the 16-bit designto a 64-bit adder using the same two component types: a 4-bit adder module and a 4-bit carry-lookahead generator. (10-marks) 18. Use the multiplier cell to construct a combinational array multiplier for 5-bit unsigned numbers. Draw a logic diagram for the multiplier and show all the signals (including constant signals) applied to every cell. (15-marks)
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19. Suppose the register file RF 16 is to be built out of four identical 4-bit slices denoted RF 4 . (a) Give a register-level diagram showing the internal structure of RF4. (b) Show how four copies of RF 4 are interconnected to form RF 16 . (15-marks) 20. Procedure gcd shown in figure is an HDL description to compute the greatest common division os two numbers. Design the gcd processor and construct a Moore-type state table defining the control unit gcd processor, an excitation table, logic equations and a complete logic circuit that uses D flip-flops and NAND gates only.(Hint: Use classical method) (20-marks) gcd (in:x,y;out:z) register XR, YR, TEMPR; XR := x; YR := y;(input the data) while XR>0 do begin if XR<=YR then begin (swap XR and YR) TEMPR := YR; XR := TEMPR; end XR := XR – YR; (subtract YR from XR ) end z := YR; (output the result) end gcd 21. The behavior of the DMA controller is given by the state transition diagram of figure. Construct the condensed state table for this controller. Obtain a state- trasition equations and output equations from your state table. Construct a typical one-hot design with all NAND gates and D Flip-flops from these equations. (20-marks)
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22. Given flowchart for the twos’ complement multiplier control unit. Construct the state table for this controller, obtain state transition equation and output equation from your state table. Construct a typical one-hot design which all NAND gates and D filp- flop. (20-marks) ` S1 C9,C10 S3 C2,C3,C4 S2 C8 S4 C0,C1,C11 S5 C2,C3,C4,C5 S6 C6 Cycle 0 Cycle 1to 7 Cycle 8 Flowchart for twos’ complement multiplier Begin A :=0 COUNT := 0 F := 0 M := INBUS Q := INBUS Q(0):= 0?
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