Module topmoduletb logic a b c w x y z instantiate

This preview shows page 5 - 6 out of 6 pages.

module topmodule_tb(); logic a, b, c, w, x, y, z; //instantiate device under test topmodule dut( a, b, c, w, x, y, z); //apply inputs one at a time initial begin a = 0; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; a = 1; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; end endmodule
Image of page 5

Subscribe to view the full document.

Constraints file For Code Converter implemented Using 7-segment Display Decoder # Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] # Switches set_property PACKAGE_PIN V17 [get_ports {inpA}] set_property IOSTANDARD LVCMOS33 [get_ports {inpA}] set_property PACKAGE_PIN V16 [get_ports {inpB}] set_property IOSTANDARD LVCMOS33 [get_ports {inpB}] set_property PACKAGE_PIN W16 [get_ports {inpC}] set_property IOSTANDARD LVCMOS33 [get_ports {inpC}] #7 segment display set_property PACKAGE_PIN W7 [get_ports {a}] set_property IOSTANDARD LVCMOS33 [get_ports {a}] set_property PACKAGE_PIN W6 [get_ports {b}] set_property IOSTANDARD LVCMOS33 [get_ports {b}] set_property PACKAGE_PIN U8 [get_ports {c}] set_property IOSTANDARD LVCMOS33 [get_ports {c}] set_property PACKAGE_PIN V8 [get_ports {d}] set_property IOSTANDARD LVCMOS33 [get_ports {d}] set_property PACKAGE_PIN U5 [get_ports {e}] set_property IOSTANDARD LVCMOS33 [get_ports {e}] set_property PACKAGE_PIN V5 [get_ports {f}] set_property IOSTANDARD LVCMOS33 [get_ports {f}] set_property PACKAGE_PIN U7 [get_ports {g}] set_property IOSTANDARD LVCMOS33 [get_ports {g}] set_property PACKAGE_PIN V7 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] set_property PACKAGE_PIN U2 [get_ports {an[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] set_property PACKAGE_PIN U4 [get_ports {an[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] set_property PACKAGE_PIN V4 [get_ports {an[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] set_property PACKAGE_PIN W4 [get_ports {an[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
Image of page 6
  • Fall '13
  • MehmetBaray
  • Berlin U-Bahn, CLK, module muxStr

{[ snackBarMessage ]}

Get FREE access by uploading your study materials

Upload your study materials now and get free access to over 25 million documents.

Upload now for FREE access Or pay now for instant access
Christopher Reinemann
"Before using Course Hero my grade was at 78%. By the end of the semester my grade was at 90%. I could not have done it without all the class material I found."
— Christopher R., University of Rhode Island '15, Course Hero Intern

Ask a question for free

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern