# Figure 1519d plots the overall vtc identifying

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as a resistor carrying a zero current. Figure 15.19(d) plots the overall VTC, identifying different regions of operations by numbers. Example 15.14 Determine a relationship between and that sets the trip point of the CMOS inverter to , thus providing a “symmetric” VTC. Solution Replacing both and with in Eq. (15.45), we have (15.49) and hence (15.50) In practice, the difference between and can be neglected with respect to . Similarly, . Also, in digital design, both and are typically chosen equal to the minimum allowable value. Thus, (15.51) Since the PMOS mobility is about one-third to one-half of the NMOS mobility, is typically twice to three times as wide as . Exercise What is the small-signal gain of the inverter under this condition? Example 15.15 Explain qualitatively what happens to the VTC of the CMOS inverter as the width of the PMOS transistor is increased (i.e., as the PMOS device is made “stronger”)? Solution Let us first consider the transition region around the trip point, where both and operate in saturation. As the PMOS device is made stronger, the circuit requires a higher input voltage to establish . This is evident from Eq. (15.45): for , as increases, must also increase so that on the right hand side decreases and on the left hand side increases. Consequently, the characteristic is shifted to the right (why?). (What happens to the small-signal gain near the trip point?) Exercise What happens to the VTC of the CMOS inverter if the PMOS device experiences resistive

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 794 (1) 794 Chap. 15 Digital CMOS Circuits degeneration? Noise Margins Recall from Example 15.6 that a digital inverter always exhibits a small- signal voltage gain greater than unity in some region of the input/output characteristic. Since the gain of a CMOS inverter falls to zero near and (why?), we expect a gain of (negative) unity at two points between and . To determine the noise margin for logical low levels, we focus on region 2 in Fig. 15.19(d). With in the triode region, the voltage gain is relatively low and likely to assume a magnitude of unity somewhere. How do we express the gain of the circuit here? In a manner similar to Example 15.7, we directly differentiate both sides of (15.43) with respect to : (15.52) The input level, , at which the gain reaches can be solved by assuming : (15.53) where denotes the corresponding output level. Obtaining from (15.53), substituting in (15.43), and carrying out some lengthy algebra, we arrive at (15.54) where (15.55) Example 15.16 Recall from Example 15.14 that a symmetric VTC results if , , and . Compute for this case. Solution Choice of in (15.54) yields . We can use L’Hopital’s rule by first writing (15.54) as (15.56) where it is assumed . Differentiating the numerator and the denominator with respect to and substituting for , we have (15.57)
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 795 (1) Sec. 15.2 CMOS Inverter 795 For example, if V and V, then V.

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