156 Electrical Specifications Copyright 20072010 Texas Instruments Incorporated

156 electrical specifications copyright 20072010

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156 Electrical Specifications Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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Lead Active Trail t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XWEL) t d(XCOHL-XWEH) t d(XCOHL-XZCSH) t en(XD)XWEL t h(XD)XWEH t dis(XD)XRNW XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XZCS0 XZCS6 XZCS7 , , XRD XWE0 XWE1 , (D) XR/W XD[0:31], XD[0:15] t d(XCOH-XRNWL) t d(XCOHL-XRNWH) DOUT XREADY (E) t d(XWEL-XD) XA[0:19] (A) (B) (C) TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transition to their inactive state. C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high. D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0. E. For USEREADY = 0, the external XREADY input signal is ignored. Figure 6-24. Example Write Access XTIMING register parameters used for this example : XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE N/A (1) N/A (1) N/A (1) 0 0 1 0 0 N/A (1) (1) N/A = Not applicable (or “Don’t care”) for this example Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 157 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.14.7 External Interface Ready-on-Read Timing With One External Wait State Table 6-41. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) PARAMETER MIN MAX UNIT t d(XCOH-XZCSL) Delay time, XCLKOUT high to zone chip-select active low 1 ns t d(XCOHL-XZCSH) Delay time, XCLKOUT high/low to zone chip-select inactive high –1 0.5 ns t d(XCOH-XA) Delay time, XCLKOUT high to address valid 1.5 ns t d(XCOHL-XRDL) Delay time, XCLKOUT high/low to XRD active low 0.5 ns t d(XCOHL-XRDH) Delay time, XCLKOUT high/low to XRD inactive high – 1.5 0.5 ns t h(XA)XZCSH Hold time, address valid after zone chip-select inactive high (1) ns t h(XA)XRD Hold time, address valid after XRD inactive high (1) ns (1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. This includes alignment cycles. Table 6-42. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) MIN MAX UNIT t a(A) Access time, read data from address valid (LR + AR) – 16 (1) ns t a(XRD) Access time, read data valid from XRD active low AR – 14 (1) ns t su(XD)XRD Setup time, read data valid before XRD strobe inactive high 14 ns t h(XD)XRD Hold time, read data valid after XRD inactive high 0 ns (1) LR = Lead period, read access. AR = Active period, read access. See Table 6-36 .
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