TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439H–JUNE 2007–REVISED MARCH 20106.14.7External Interface Ready-on-Read Timing With One External Wait StateTable 6-41. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)PARAMETERMINMAXUNITtd(XCOH-XZCSL)Delay time, XCLKOUT high to zone chip-select active low1nstd(XCOHL-XZCSH)Delay time, XCLKOUT high/low to zone chip-select inactive high–10.5nstd(XCOH-XA)Delay time, XCLKOUT high to address valid1.5nstd(XCOHL-XRDL)Delay time, XCLKOUT high/low to XRD active low0.5nstd(XCOHL-XRDH)Delay time, XCLKOUT high/low to XRD inactive high– 1.50.5nsth(XA)XZCSHHold time, address valid after zone chip-select inactive high(1)nsth(XA)XRDHold time, address valid after XRD inactive high(1)ns(1)During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. Thisincludes alignment cycles.Table 6-42. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)MINMAXUNITta(A)Access time, read data from address valid(LR + AR) – 16(1)nsta(XRD)Access time, read data valid from XRD active lowAR – 14(1)nstsu(XD)XRDSetup time, read data valid before XRD strobe inactive high14nsth(XD)XRDHold time, read data valid after XRD inactive high0ns(1)LR = Lead period, read access. AR = Active period, read access. SeeTable 6-36.
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Serial Peripheral Interface Bus, Texas Instruments Incorporated, TMS320F28335