GPIO28SCIRXDAXZCS6 GPIO34ECAP1XREADY V DDIO V SS GPIO36SCIRXDAXZCS0 V DD V SS

Gpio28scirxdaxzcs6 gpio34ecap1xready v ddio v ss

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GPIO28/SCIRXDA/XZCS6 GPIO34/ECAP1/XREADY V DDIO V SS GPIO36/SCIRXDA/XZCS0 V DD V SS GPIO35/SCITXDA/XR/W XRD GPIO37/ECAP2/XZCS7 GPIO40/XA0/XWE1 GPIO41/XA1 GPIO42/XA2 V DD V SS GPIO43/XA3 GPIO44/XA4 GPIO45/XA5 V DDIO V SS GPIO46/XA6 GPIO47/XA7 GPIO80/XA8 GPIO81/XA9 GPIO82/XA10 V SS V DD GPIO83/XA11 GPIO84/XA12 V DDIO V SS GPIO85/XA13 GPIO86/XA14 GPIO87/XA15 GPIO39/XA16 GPIO31/CANTXA/XA17 CIRXDA/XZCS6 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 2.1 Pin Assignments The 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1 . The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5 . The 176-ball ZJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 through Figure 2-9 . Table 2-3 describes the function(s) of each pin. Figure 2-1. F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) Copyright © 2007–2010, Texas Instruments Incorporated Introduction 15 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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ADCINB0 ADCINB2 ADCINB6 ADCREFP ADCINA1 ADCRESEXT ADCINA2 ADCLO ADCINA0 ADCINB4 V SS1AGND ADCINA4 ADCINA3 ADCINB3 ADCREFIN P P N N M M L L ADCINA5 GPIO18/ SPICLKA/ SCITXDB/ CANRXA V SSA2 ADCINA7 ADCINB7 GPIO17/ SPISOMIA/ CANRXB/ TZ6 V DD1A18 V DD GPIO14/ / SCITXDB/ MCLKXB TZ3 XHOLD/ GPIO13/ CANRXB/ MDRB TZ2/ V DDAIO K K J J H H 1 2 3 4 5 6 7 GPIO20/ EQEP1A/ MDXA/ CANTXB V SS2AGND GPIO21/ EQEP1B/ MDRA/ CANRXB GPIO22/ EQEP1S/ MCLKXA/ SCITXDB V SS 1 2 3 4 5 6 7 V SSAIO V SS V DD V DD GPIO23/ EQEP1I/ MFSXA/ SCIRXDB GPIO19/ SCIRXDB/ CANTXA SPISTEA/ ADCINA6 GPIO16/ SPISIMOA/ CANTXB/ TZ5 GPIO15/ / SCIRXDB/ MFSXB TZ4 XHOLDA/ V DDA2 V DD2A18 ADCREFM ADCINB5 ADCINB1 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 NOTE The powerpad on the bottom side of the PTP package is not connected to the ground (GND) of the die. Proper thermal management of the PowerPAD™ package requires PCB preparation. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD package. The size of the thermal land should be as large as needed to dissipate the required heat. Note that the PowerPAD package with exposed pad down must be soldered to the PCB. Refer to the PowerPAD™ Thermally Enhanced Package Application Report (literature number SLMA002 ) for more details on using the PowerPAD package. Figure 2-2. F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) 16 Introduction Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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GPIO50/ EQEP1A/ XD29 TMS TEST2 EMU1 GPIO51/ EQEP1B/ XD28 GPIO48/ ECAP5/ XD31 TCK GPIO52/ EQEP1S/ XD27 V SS GPIO27/ ECAP4/ EQEP2S/ MFSXB XRS EMU0 GPIO53/ EQEP1I/ XD26 V DD GPIO55/ SPISOMIA/ XD24 V SS GPIO56/ SPICLKA/ XD23 GPIO58/ MCLKRA/ XD21 GPIO33/ SCLA/ EPWMSYNCO/ ADCSOCBO TRST GPIO32/ SDAA/ EPWMSYNCI/ ADCSOCAO V DDIO 8 9 10 11 12 13 14 P P N N M M L L K K J J H H GPIO57/ / XD22 SPISTEA X1 XCLKIN GPIO59/ MFSRA/ XD20 V SS GPIO25/ ECAP2/ EQEP2B/ MDRB V SS V DD V SS 8 9 10 11 12 13 14 V SS V SS TEST1 V DD3VFL GPIO24/ ECAP1/ EQEP2A/ MDXB GPIO26/ ECAP3/ EQEP2I/
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