Attribute instructionprivate of asicp entity is

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-- attribute INSTRUCTION_PRIVATE of asic_p : entity is " " attribute IDCODE_REGISTER of asic_p : entity is "0000" & -- 4-bit version "0000000000000000" & -- 16-bit part number "00000101011" & -- 11-bit manufacturer "1"; -- mandatory LSB -- attribute USERCODE_REGISTER of asic_p : entity is " " attribute REGISTER_ACCESS of asic_p : entity is "BOUNDARY (STCTEST)"; attribute BOUNDARY_CELLS of asic_p : entity is "BC_1, BC_2"; attribute BOUNDARY_LENGTH of asic_p : entity is 2; attribute BOUNDARY_REGISTER of asic_p : entity is -- num cell port function safe [ccell disval rslt] " 1 ( BC_2, pad_a(0), input, X)," & " 0 ( BC_1, pad_z(0), output2, X)"; -- " 98 ( BC_1, OE, input, X), " & -- " 98 ( BC_1, *, control, 0), " & -- " 99 ( BC_1, myport(0), output3, X, 98, 0, Z); end asic_p; The functions of the lines of this BSDL description are as follows: Line 2 refers to the ASIC package. We can have the same part (with identical pad numbers on the silicon die) in different ASIC packages. We include the name of the ASIC package in line 2 and the pin mapping between bonding pads and ASIC package pins in lines 14 21 .
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Lines 3 10 describe the signal names of inputs and outputs, the TAP pins, and the optional fifth TAP reset signal. The BST signals do not have to be given the names used in the standard: TCK, TDI, and so on. Line 11 refers to the VHDL package, STD_1149_1_1994 . This is a small VHDL package (just over 100 lines) that contains definitions of the constants, types, and attributes used in a BSDL description. It does not contain any models for simulation. Lines 22 25 attach signal names to the required TAP pins and the optional fifth TAP reset signal. Lines 26 27 refer to the maximum test clock frequency in hertz, and whether the clock may be stopped in both states or just the low state (just the high state is not valid). Line 28 describes a 3-bit IR (in the comparator/MUX example we used a 2-bit IR). Length must be greater than or equal to 2. Lines 29 35 describe the three required instruction opcodes and mnemonics ( BYPASS, SAMPLE, EXTEST ) and three optional instructions: IDCODE, STCTEST (which is a scan test mode), and INTEST (which supports internal testing in the same fashion as EXTEST supports external testing). EXTEST must be all ones; BYPASS must be all zeros. A mnemonic may have more than one opcode (and opcodes may be specified using 'x' ). Other instructions that may appear here include CLAMP and HIGHZ , both optional instructions that were added to 1149.1 (see Supplement A, 1149.1a). String concatenation is used in BSDL to avoid line-break problems. Lines 37 39 include instruction attributes INSTRUCTION_DISABLE (for HIGHZ ), INSTRUCTION_GUARD (for CLAMP ), as well as INSTRUCTION_PRIVATE (for user-defined instructions) that are not used in this example. Lines 40 44 describe the IDCODE TDR. The 11-bit manufacturer number is determined from codes assigned by JEDEC Publication 106-A.
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  • Fall '15
  • prasad
  • TCK, TDO, tap controller

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