22.11. Register DescriptionAtmel ATmega328/P [DATASHEET]Atmel-42735A-ATmega328/P_Datasheet_Complete-06/2016202
22.11.1. TC2 Control Register AName: TCCR2AOffset: 0xB0Reset: 0x00Property:-Bit76543210COM2A1COM2A0COM2B1COM2B0WGM21WGM20AccessR/WR/WR/WR/WR/WR/WReset000000Bits 7:6 – COM2An: Compare Output Mode for Channel A [n = 1:0]These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0] bits areset, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However,note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order toenable the output driver.When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[2:0] bitsetting. The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to anormal or CTC mode (non- PWM).Table 22-3. Compare Output Mode, non-PWMCOM2A1COM2A0Description00Normal port operation, OC2A disconnected.01Toggle OC2A on Compare Match.10Clear OC2A on Compare Match.11Set OC2A on Compare Match .The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWMmode.Table 22-4. Compare Output Mode, Fast PWM(1)COM2A1COM2A0Description00Normal port operation, OC2A disconnected.01WGM22 = 0: Normal Port Operation, OC2A DisconnectedWGM22 = 1: Toggle OC2A on Compare Match10Clear OC2A on Compare Match, set OC2A at BOTTOM (non-inverting mode)11Set OC2A on Compare Match, clear OC2A at BOTTOM (inverting mode)Note: 1.A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case the comparematch is ignored, but the set or clear is done at BOTTOM. Refer toFast PWM Modefor details.The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phasecorrect PWM mode.Atmel ATmega328/P [DATASHEET]Atmel-42735A-ATmega328/P_Datasheet_Complete-06/2016203
Table 22-5. Compare Output Mode, Phase Correct PWM Mode(1)COM2A1COM2A0Description00Normal port operation, OC2A disconnected.01WGM22 = 0: Normal Port Operation, OC2A Disconnected.WGM22 = 1: Toggle OC2A on Compare Match.10Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Matchwhen down-counting.11Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Matchwhen down-counting.Note: 1.A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the CompareMatch is ignored, but the set or clear is done at TOP. Refer toPhase Correct PWM Modefordetails.Bits 5:4 – COM2Bn: Compare Output Mode for Channel B [n = 1:0]These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B[1:0] bits areset, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However,note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order toenable the output driver.
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