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2.Select IC Compiler, and then select a release in the list that appears.About This GuideThe IC Compiler tool provides a complete netlist-to-GDSII or netlist-to-clock tree synthesis design solution, which combines proprietary design planning, physical synthesis, clock tree synthesis, and routing for logical and physical design implementations throughout the design flow.This guide describes the IC Compiler design planning flow; the companion volume, IC Compiler Implementation User Guide, describes the implementation and integration flow.AudienceThis user guide is for design engineers who use IC Compiler to implement designs.To use IC Compiler, you need to be skilled in physical design and design synthesis and be familiar with the following:•Physical design principles•The Linux or UNIX operating system•The tool command language (Tcl)
PrefaceAbout This GuidexviiIC Compiler Design Planning User GuideVersion D-2010.03-SP4Related PublicationsFor additional information about IC Compiler, see Documentation on the Web, which is available through SolvNet at the following address:You might also want to see the documentation for the following related Synopsys products:•Design Compiler•Milkyway Environment
PrefaceAbout This GuidexviiiIC Compiler Design Planning User GuideD-2010.03-SP4IC Compiler Design Planning User GuideVersion D-2010.03-SP4ConventionsThe following conventions are used in Synopsys documentation.ConventionDescriptionCourierIndicates command syntax.Courier italicIndicates a user-defined value in Synopsys syntax, such as object_name. (A user-defined value that is not Synopsys syntax, such as a user-defined value in a Verilog or VHDL statement, is indicated by regular text font italic.)Courier boldIndicates user input—text you type verbatim—in Synopsys syntax and examples. (User input that is not Synopsys syntax, such as a user name or password you enter in a GUI, is indicated by regular text font bold.)[ ]Denotes optional parameters, such as pin1 [pin2 ... pinN]|Indicates a choice among alternatives, such as low | medium | high(This example indicates that you can enter one of three possible values for an option: low, medium, or high.)_Connects terms that are read as a single term by the system, such as set_annotated_delayControl-cIndicates a keyboard combination, such as holding down the Control key and pressing c.\Indicates a continuation of a command line./Indicates levels of directory structure.Edit > CopyIndicates a path to a menu command, such as opening the Edit menu and choosing Copy.
PrefaceCustomer SupportxixIC Compiler Design Planning User GuideVersion D-2010.03-SP4Customer SupportCustomer support is available through SolvNet online customer support and through contacting the Synopsys Technical Support Center.
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Electronic design automation, Design closure, ic compiler, design planning