EEE6323S12-HLec03-CMOS-Layout-4spp

M1 v dd and gnd rails • m2 access to i/os • well

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Unformatted text preview: M1 V DD and GND rails • M2 Access to I/Os • Well / substrate taps • Exploits regularity Wiring Tracks • A wiring track is the space required for a wire – 4 λ width, 4 λ spacing from neighbor = 8 λ pitch • Transistors also consume one wiring track • Estimate area by counting wiring tracks Stick Diagrams • Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers 3 Example: O3AI • Sketch a stick diagram for O3AI and estimate area – ( ) Y A B C D = + + g Optimal POLY Ordering • Define Euler path – Uninterrupted path that traverses each edge of the graph EXACTLY ONCE • Find Euler path in PDN and PUN graph below starting at x. . x What is the order of inputs for the common Euler paths? Example • Determine the graph for the PDN and PUN for • Find the Euler path . A B C D E F F = (A + BC + D)(E + F) C B A E F D GND VDD F C B D F E A GND VDD F Stick Diagram 4 Y-Diagram: Design Partitioning Physical Design datapath control er alucontrol ph1 ph2 reset memdata[7:0] writedata[7:0] adr[7:0] memread memwrite op[5:0] zero pcen regwrite irwrite[3:0] memtoreg iord pcsource[1:0] alusrcb[1:0] alusrca aluop[1:0] regdst funct[5:0] alucontrol[2:0] Example: 8-bit processor PC M u x 1 Registers Write...
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