h ierarchical references to imported identifiers are allowed as if they are

H ierarchical references to imported identifiers are

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h ierarchical references to imported identifiers are allowed as if they are defined in the importing scope E xplicit import like a local declaration m ultiple identical allowed module my_design (); my_global_stuff_pkg::traffic_stop_t my_traffic_stop; module my_design (); import my_global_stuff_pkg::*; Advanced Hardware Design & Verification SystemVerilog
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package ComplexPkg; typedef struct { float i, r; } Complex; Complex C_data = ‘{i:2.0, r:5.7}; function Complex ADD (Complex a, b) ADD.r = a.r + b.r; ADD.i = a.i + b.i; endfunction : ADD function Complex MULT (Complex a, b) MULT.r = (a.r * b.r) + (a.i * b.i); MULT.i = (a.r * b.i) + (a.i * b.r); endfunction : MULT endpackage : ComplexPkg [ Verification] Data - Types package s Importing - Examples [email protected] 25 ComplexPkg::C_data = ComplexPkg::MULT(a, b); import ComplexPkg::C_data; initial C_data = ‘{i:6.0,r:2.7}; import ComplexPkg::*; initial C_data = ADD(a, b); Advanced Hardware Design & Verification SystemVerilog
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[ Verification] Data - Types ( classes_pkg.sv ) for a De - Bouncer Complete Example package classes_pkg; class PushButton; // Class Properties rand bit [31:0] delay; constraint c_delay {delay > 20; // Delay is > than 20 ns delay < 7000000;} // Delay is < 7 ms function new ( ); delay = 0; endfunction endclass : PushButton endpackage : classes_pkg [email protected] 26 module key_bfm (clk, reset, key); output key; input reset, clk; // Import Classes import classes_pkg::*; // Define local Variables reg key; PushButton key_obj; task push_button( ); time delay; begin key_obj.randomize ( ); delay = key_obj.delay; key = 1'b1; # delay key = 1'b0; end endtask initial begin key = 1'b0; key_obj = new ( ); end endmodule : key_bfm Advanced Hardware Design & Verification SystemVerilog
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[ Verification] Data - Types User - Defined Structures struct typedef struct { int hw_grade_1; int hw_grade_2; int hw_grade_1; int hw_grade_2; int hw_grade_5; } hw_grades_s; S uppose you want to group variables into a block or a structure. you can do so by using a struct keyword. It’s functionality is similar to that of other programming languages. Structure and union declarations follow the C syntax, but without the optional structure tags before the ‘{‘. I t is recommended that you start appending your new variables with their associated type. For example, we use the postfix “ _s ” to indicate a structure data type. struct { bit [7:0] opcode; bit [23:0] addr; } IR; // anonymous structure // defines variable IR IR.opcode = 1; // set field in IR. W e can define struts' that are user-defined data-types. W e can create a variable structure. [email protected] 27 Advanced Hardware Design & Verification SystemVerilog
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[ Verification] Data - Types Constants Example Code and explanation [email protected] 28 initial begin const byte colon = “:”; ... end Pages: 61 A const form of constant differs from a localparam constant in that the localparam must be set during elaboration, whereas a const can be set during simulation, such as in an automatic task. [SVLRM] initial begin ...
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