Survey of Hardware Systems for Wireless Sensor Networks Hempstead et al 8 bit

Survey of hardware systems for wireless sensor

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Survey of Hardware Systems for Wireless Sensor Networks Hempstead et al. 8-bit datapath with separate instruction and data memories, a decode and fetch stage, and logic for event scheduling. The authors implemented two versions of the Sublimi- nal processor in 130 nm CMOS. Because standard bitline- based SRAMs do not function reliably in subthreshold, the prototypes used mux based memories. In both versions the authors measured significant delay variability when oper- ating in subthreshold. The normalized maximum operating frequency of the first prototype varied from 0.6 to 1.8 at 260 mV across a distribution of 26 different chips. 28 The average energy consumption of the subliminal processor is 2.6 pJ/inst and 3.5 pJ/inst. 4.4. Asynchronous—SNAP The SNAP processor from Cornell is an asynchronous 16-bit RISC based processor designed with sensor network workloads in mind. 4 5 12 SNAP is an event-driven processor by design and includes two accelerators that generate WSN specific events. SNAP uses quasi delay-insensitive (QDI) circuits (defined in Section 3.2). By designing SNAP com- pletely with asynchronous circuits, it runs across a wide range of supply voltage from 1.8 V to 0.6 V. Figure 3 presents a simplified block diagram of SNAP/LE, the first implementation of the SNAP archi- tecture. SNAP does not perform computation continu- ously but instead responds to discrete events . The system includes an event queue containing tokens that designate a particular event. When the token reaches the head of the queue, SNAP fetches the corresponding event han- dler from instruction memory (IMEM). The decode block selects the appropriate execution unit for the opcode and gets operands from data memory (DMEM) and the regis- ter file. The instructions are processed in sequence until the “done” instruction is reached indicating the end of the event handler . If the event queue is empty, SNAP stalls after reaching the “done” instruction and waits for a new event token to enter the event queue. Event Queue Fig. 3. Simplified block diagram of the SNAP processor for WSN. Sys- tem includes separate instruction and data memories, a timer coprocessor, and a message processor which provides a FIFO interface to the off-chip radio and sensors. Reprinted with permission from [4], V. Ekanayake et al., An ultra low-power processor for sensor networks. Proceedings of the 11th International Conference on Architectural Support for Program- ming Languages and Operating Systems , Boston, MA, October (2004) . © 2004. SNAP includes two components that generate events, the timer coprocessor and message coprocessor. The timer coprocessor consists of three self-decrementing timer reg- isters; it posts a timer event token when the registers reach zero. The message coprocessor serves as the inter- face between SNAP and off-chip devices by providing I/Os for sensors and the radio. SNAP communicates with the message coprocessor through a single register. Each time a byte arrives on the radio, the message coprocessor posts an event to the event queue. The message coprocessor does
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  • Fall '18
  • Mr. Bhullar
  • Sensor node, Wireless sensor network

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