23.The accumulator based CPU consists of a datapath unit DPU designed to execute the set of in basic single-address instructions as follow: Data Transfer LDX STX MOV DR, AC MOV AC,DR Data Processing ADD SUB AND NOT Program Control BRA adr BZ adr Draw the flow chart describing the behavior of this CPU. (10-marks) 24. Design the typical microprogrammed controller including multiplexer, microprogrammed counter, control memory and decoder. Use the following microinstrction format. (10-marks) 25. Construct the basic structure of microprogrammed control unit. (20-marks) 26. Show how to connect three copies of the 2909 (4-bit microprogrammed sequencer) to form a 12-bit address. (10marks) 27. Draw a structure of microprogrammed control unit for the twos’ complement multiplier. (10marks) 28.Show how to construct four slice 2901 array configure to form a 16-bit multiplication. (10marks) 29. Express the microprogrammed emulator for following small instruction set. FETCH LD ST ADD SUB AND NOT BRA BZ MOV-2 (10marks) 30.Difference between horizontal versus vertical of microinstruction types. (5-marks) 31.Difference between classical method and one-hot method. (5-marks)
32.Construct the state table corresponding to the state transition graph of figure. Is this a Mealy (or) Moore machine? (5-marks) 33. Draw the CPU organization that implements a four-state instruction pipeline, what function of four stages. (10marks)
has intentionally blurred sections.
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