11 To run the program Debug Run 12 Observe the output in output window 13 To

11 to run the program debug run 12 observe the output

This preview shows page 33 - 36 out of 49 pages.

11. To run the program Debug Run 12. Observe the output in output window. 13. To see the Graph go to View and select time/frequency in the Graph, and give the correct Start address provided in the program, Display data can be taken as per user
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DEE, CEME (NUST), Rawalpindi EE-330 Digital Signal Processing 34 Task: No specific task for this lab except reading and practice of the tutorial Conclusion: In this lab DSP kits were discussed, along with their advantage, versatility and flexibility. Introduction to Code Composer Studio was completed along with a sample example.
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DEE, CEME (NUST), Rawalpindi EE-330 Digital Signal Processing 35 Lab 7(DSP Kit): Data Acquisition, Usage and Operation of I/O Available on DSKC6713 Introduction to the TMS320C6713 DSP Device The Texas Instruments TMS320C6000 DSP platform of high-performance digital signal processors (DSPs) now includes the TMS320C6713. The C6713 brings the highest level of performance in the C6000 DSP platform of floating-point DSPs. At the initial clock rate of 225 MHz, the C6713 can process information at a rate of 1.35 giga-floating-point operations per second (GFLOPS). Introduced in February 1997, the C6000 DSP platform is based on TI’s VelociTI architecture, an advanced very- long-instruction-word (VLIW) architecture for DSPs. Advanced features of the VelociTI architecture include instruction packing, conditional branching, and pre- fetched branching, all of which overcome problems that were associated with previous VLIW implementations. The architecture is highly deterministic, with few restrictions on how or when instructions are fetched, executed, or stored. This architectural flexibility is key to the breakthrough efficiency levels of the C6000 compiler. TMS320C6000 Compatibility All C6000 DSP platform devices are code-compatible with one another, with the exception that there are some floating-point instructions that are only valid on the floating-point (TMS320C67x ) members. The C67x DSP core employs the VelociTI architecture that is designed to achieve high performance through increased instruction-level parallelism. VelociTI provides eight execution units, including two multipliers and six arithmetic logic units (ALUs). Out of eight functional units, six (L1, L2, S1, S2, M1, and M2) can perform six floating-point operations every cycle. These functional units operate in parallel and can perform up to eight instructions, including six floating-point operations during a single clock cycle—up to 1800 million instructions per second (MIPS), or 1.35 GFLOPS at 225 MHz initial device clock speed. The common architecture allows designers to begin development with existing C6000 software tools for those devices currently in development. This also allows for migration from one C6000 processor to another, as design specifications require. In addition to the DSP core, many of the on-chip peripherals are common between C6000 devices. Figure 2 shows a block diagram of the C6713 device. The blocks in white are common among members of C6700 generation of floating-point DSPs. The blocks in gray are new peripheral/improved features available on the C6713 device.
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