Mosfets understand the terminal i v characteristics

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(MOSFETs); understand the terminal I-V characteristics of both enhancement mode and depletion mode MOSFETs; design circuits containing MOSFETs, analyze for gain, input and output resistance and be able to apply the small-signal model; understand the operation of both NMOS and CMOS digital logic inverters, NAND gates and NOR gates; iii. Bipolar Junction Transistors: Understand the physical structure and operation of BJTs; analyze different transistor properties by using the small-signal BJT model; design bias circuits for operating BJTs in the linear region; analyze gain, input and output resistance of various amplifiers; design common-emitter, common-base, common collector amplifiers and saturated switches using BJTs; iv. Op Amps: Analyze circuits containing ideal op amps; understand the effects of non-ideal op-amp characteristics on circuits; design op-amp buffers, inverting/noninverting amplifiers, summers, integrators, differentiators, instrumentation amps and comparators. B. Become proficient with computer skills (e.g. Multisim) for the analysis and design of circuits. C. Learn technical writing skills important for effective communication. D. Develop teamwork skills for working effectively in groups. 7. Grading Policy Lecture Related: Homework 10% Exam 1 20% Exam 2 20% Final Exam 20% Laboratory Related : Lab Notebook and Design Projects 25% Attendance and Participation : In lecture and in lab 5% Totals: 100% The grading scale is as follows: A 90-100 A- 87-90 B+ 84-87 B 80-84 B- 78-80 C+ 74-78 C 70-74 D 60-70 F <60 In accordance with EE Department policy, a grade of “C” or better (nominally a 70% average) is required in this course to graduate with a degree in Electrical Engineering.
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4 Rev. A - 1/5/2019 8. Attendance We will take attendance and your record of attendance will be considered when assigning grades. Attendance at lectures and labs will comprise 5% of your overall grade in the course. You may attend either lecture; the same attendance sheet is used at each lecture. Attendance is also taken at each lab and you will receive a zero for that lab if you are not present. If you arrive late or leave early you will receive a grade penalty for that lab. If you have a legitimate conflict with a scheduled lab you must notify your TA and lab partner(s) in advance. For last-minute emergencies (illness, etc.), you must notify your instructor and/or TA via email. In this course, attendance is not optional; it is required . 9. Evening Exams There are two Monday evening exams scheduled for EE 310. See the course schedule for the dates and times. Add these to your personal calendar now. Before the end of the drop/add period, you must determine if you have a conflict with the exam dates and times, or if you need special service with letter from ODS. If you do, complete the conflict exam application form. Note 1. If you do not file your request on time then you will not be permitted to take a conflict exam.
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  • Spring '07
  • WHARTON,MARKJEDWARDS,PERRYSTO
  • Integrated Circuit, TA, Design Projects, Tian Zhang, Reza Nouri

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