Virtual routes for nets crossing a voltage area do not zigzag in and out of the

Virtual routes for nets crossing a voltage area do

This preview shows page 760 - 762 out of 964 pages.

Virtual routes for nets crossing a voltage area do not zigzag in and out of the voltage area: the number of boundary crossings is minimized. Also, routing-driven synthesis, such as maximum net length optimization, uses voltage-area-aware routing. Maximum Net Length Optimization The maximum net length optimization carried out by the psynopt command takes into account the presence of voltage areas, basically routing around them. Routes for nets connecting two cells within a voltage area stay inside the voltage area, and routes for nets crossing into a voltage area do not excessively zigzag in and out of the voltage area. Voltage-Area-Based Optimization Cell placement and buffer optimization is one-pass voltage-area-aware. When the tool buffers a net that crosses voltage areas, the net is divided into multiple segments, each of which is confined within a single voltage area (including the default voltage area), and buffering is confined to the segments. The insertion of new buffers does not introduce additional zigzag paths that cross the voltage area boundaries. For designs with multiple voltage areas, the tool ensures that a tie cell in one voltage area does not feed a cell in another voltage area. You should ensure that constant nets remain within their respective voltage area boundaries. If the direct_power_rail_tie attribute has been set on a library pin, instances of this pin do not connect to constant signals by connecting to a tie-off cell. Instead, such pins are connected to generic constant signals so that during power routing these pins can be connected directly to power rails.
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Chapter 14: Multivoltage Design Flow Voltage-Area-Aware Capabilities 14-57 IC Compiler Implementation User Guide Version D-2010.03-SP4 Voltage-Area-Based Clock Tree Synthesis and Optimization Clock tree synthesis and optimization are voltage-area-aware; they honor the following constraints: Sink pins are separated and clustered by voltage areas so that clock subtrees are built for each voltage area. A guide buffer is inserted for the set of sink pins for each voltage area to ensure that any subsequent levels of clustering do not mix pins from different voltage areas. After the clock subtrees are built for each voltage area, clock tree synthesis can proceed in the usual manner, joining the subtrees at the root of the clock net. In addition to the synthesis of the initial clock tree, the constraints that are listed previously are also honored by several clock tree optimization techniques, such as buffer relocation, buffer sizing, gate relocation, and delay insertion. Voltage-Area-Based Global Routing As with virtual hierarchy routing, global routing also takes the presence of voltage areas into account. The global router and the detail router observe the following constraints: Routes for nets connecting cells within a voltage area do not go outside the voltage area.
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