Are the mismatches on bi directional signals and do the differences involve

Are the mismatches on bi directional signals and do

This preview shows page 868 - 874 out of 939 pages.

Are the mismatches on bi-directional signals, and do the differences involve actual or expected “Z” values? In this type of situation, review the state of the tristate enable lines. Are the mismatches “hard errors” - for instance, an expected “1” but an actual “0” or vice-versa? This could be caused by timing problems in the design, or strobe positioning, or extra or missing clocks, glitches, or transients in the design that are causing the wrong state to appear too soon or too late compared to what the expected state was.
Image of page 868
ATPG Pattern Validation TetraMAX 1 8-32 © 2005 32 8- Consult Test Pattern Validation Guide Chapter 3, “Troubleshooting Verilog DPV”
Image of page 869
ATPG Pattern Validation TetraMAX 1 8-33 © 2005 33 8- ATPG Pattern Validation Perform STA First: z Tips for proper test STA using Primetime Simulate Patterns with DPV: z Tips for DPV Troubleshooting Patterns to ATE: z Options for handling ATE failures Test Mode STA Patterns to ATE Simulate Patterns
Image of page 870
ATPG Pattern Validation TetraMAX 1 8-34 © 2005 34 8- Real Silicon Can Still Experience Failures Even with perfect STA and simulation of a DUT model with no mismatches: actual DUTs can still fail on ATEs If the same ATE timing and post-route SDF is used in both STA and Simulation, and STA reports no violations: z Simulation mismatches can still occur due to Simulation mode (zero, unit, typical) issues ATPG results predicted based on 0-delay environment Simulation model may not match ATPG model
Image of page 871
ATPG Pattern Validation TetraMAX 1 8-35 © 2005 35 8- Not Making Any Progress in Debugging? If the mismatches and failures are localized and not widespread, one option is to use PI/POMasks, Cell Constraints and Capture Masks: z Reduce simulation mismatches z Reduce ATE false negatives Perform these in TetraMAX rather than ATE s/w: z Determine reduction in fault coverage Will the project manager or customer relax the schedule so you can perform more debugging?
Image of page 872