Solution 5n10 Question 6 10 points Suppose you have a data cache that holds

# Solution 5n10 question 6 10 points suppose you have a

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lines.2. Calculate the block offset bits = 7 bits.3. Calculate the number of sets = 210/8 = 27sets.4. Calculate the number of index bits = 7.5. Calculate the number of tag bits = 64-7-7 = 50 bits.6. Total number of bits to realize cache = 210 sets * (50 tag bits + 1 valid bit) + 128KB data.How many bits are required to implement this cache if it also caches instructions?
100))] = 16 cycles.No change for either replacement policy since we’ve already given you the hit rates.Question 8 (5 points)The goal of a cache is to improve the average memory access time or AMAT. Our objective is to quicklyascertain how cache design decisions might affect AMAT.1. Express AMAT as a function of hit time, miss rate, and miss penalty.SolutionAMAT = Hit Time + Miss Rate * Miss Penalty.2. Suppose we choose to increase the associativity of the cache from a direct-mapped to a 4-way associa-tive. How do you expect hit time, miss rate, and miss penalty parameters to change, in general? Morespecifically, for a workload with 100% cache hit rate, how do you expect AMAT to change?
3. Suppose we choose to increase the cache replacement policy from FIFO to LRU, for a 4-way associativecache. How do you expect the hit time, miss rate, and miss penalty parameters to change, in general?1. Suppose that you have the following piece of code.for (i = 0; i < n; i++) {for (j = 0; j < n; j++) {sum = 0.0;for (k = 0; k < n; k++)sum += a[i][k]*b[k][j];c[i][j] = sum;}}Suppose that the cache line size is 64 bytes and that an int data type is 4 bytes. Suppose that arraysa,b, andc, are of typeint, and constitute massive arrays that are far bigger than the size of thecache in total. Furthermore, suppose that thesumvariable is placed in a register, so does not requirememory accesses.What are the cache hit rates of accessing arraysa,b, andc