A ring oscillator can be modeled in a straightfor ward fashion by a tuple of

A ring oscillator can be modeled in a straightfor

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and “1” else. A ring oscillator can be modeled in a straightfor- ward fashion by a tuple of frequencies . Its output on input is “0” if , and “1” else. D. Numeric CRP Generation, Prediction Error, and Number of CRPs Given a PUF-architecture that should be examined, the chal- lenge-response pairs (CRPs) that we used in our ML experi- ments were generated in the following fashion: (i) The delay values for this PUF architecture were chosen pseudo-randomly according to a standard normal distribution. We sometimes refer to this as choosing a certain PUF instance in the paper. (ii) If a response of this PUF instance to a given challenge is needed, the above delays of the two electrical signal paths are simply added up and compared. This methodology follows the well-es- tablished linear additive delay model for PUFs [9], [24], [23], [17], [31], [26]. In case of the RO PUF, the frequencies were simply chosen at random according to a normal distribution. We use the following de fi nitions throughout the paper: The prediction error is the ratio of incorrect responses of the trained ML algorithm when evaluated on the test set. For all appli- cations of LR, the test set each time consisted of 10,000 ran- domly chosen CRPs. For all applications of ES (i.e., for the Feed-Forward Arbiter PUF), the test set each time consisted of 8,000 randomly chosen CRPs. The prediction rate is . (or simply “CRPs”) denotes the number of CRPs em- ployed by the attacker in his respective attack, for example in order to achieve a certain prediction rate. This nomenclature holds throughout the whole paper. Nevertheless, one subtle dif- ference should be made explicit: In all applications of LR (i.e., in Sections III to V), is equal to the size of the training set of the ML algorithm, as one would usually expect. In the appli- cations of ES (i.e., in Section VI), however, the situation is more involved. The attacker needs a test set himself in order to deter- mine which of his many random runs was the best. The value given in the tables and formulas of Section VI hence re- fl ects the sum of the sizes of the training set and the test set employed by the attacker. E. FPGA CRP Collection To obtain CRP data from FPGAs, ten independent instances of Arb-PUFs have been implemented on Spartan-6 FPGAs. The Arb-PUFs were composed of 64 pairs of multiplexers (MUXs) and a D fl ip- fl op based arbiter, and were implemented in Verilog. In order to balance FPGA routing asymmetries, which would otherwise dominate the effect of manufacturing variations, a lookup table (LUT) based Programmable Delay Line (PDL) has been implemented, as suggested by Majzoobi et al. [28], [29]. We collected 200,000 CRPs from each of our ten FPGA Arb- PUFs instances, resulting in two million CRPs altogether. For each CRP, majority voting over fi ve repetitive measurements of the response to the same challenge was performed in order to
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RÜHRMAIR et al. : PUF MODELING ATTACKS ON SIMULATED AND SILICON DATA 1881 determine the fi nal response. For example, if the fi ve measure- ments resulted in three “0”s and two “1”s, the fi nal response was set to “0”. The challenges were generated by a 64-bit pseudo-
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