inherently reduces some of the issues with high speed signaling due to the

Inherently reduces some of the issues with high speed

This preview shows page 289 - 291 out of 300 pages.

inherently reduces some of the issues with high-speed signaling due to the embedded clock, differential pairs, and point-to-point topology, but still presents a major challenge. One of the key decisions due to the faster signaling is whether or not to perform simulations of the motherboard layout. Simulations allow the vendor to predict how the system will operate prior to manufacturing. Modeling signal integrity, via HSPCIE or ISBIS, is an excellent tool to ana- lyze the board and repair potentially fatal mistakes prior to manufactur- ing. Given the fact that PCI Express is up to five times faster than anything on the current PC, vendors need to consider expanding their simulation capabilities and factor in variables currently not accounted for. For example, PCB traces account for the majority of signal degradation in most cases. At the PCI Express signaling rate, traces look less and less like a connection between two devices and more like a transmission line with significant capacitance and inductance. The PCI Express specification de- fines the channel from the device package to the connector, so every- thing in between must be considered. Previous technologies did not require this level of signal analysis. Figure 14.10 is a diagram of a side view of a 4-layer motherboard to highlight all the potential causes for
Image of page 289
290 PCI Express: A Hardware & Software Developers Guide signal deformation that are trivial for most PCI implementations. Unlike previous technologies, vendors can no longer ignore the affects of Vias, capacitive parasitics, and connectors. Device Package PCB Traces Series Capacitor Signal Layer Prepreg Power Layer Core Ground Layer Prepreg Signal Layer Signal Route VIA Connector Figure 14.10 Side View of a 4-layer Motherboard Technology transitions create both the opportunity and the necessity to revisit all of the previous operating assumptions. Vendors should re- visit their test, debug, and manufacturing capabilities in light of a new technology. Refer to Chapter 12 for implementation specifics. Conclusion Hopefully, this book has helped show that PCI Express is an exciting new architecture that will help move both the computing and communi- cations indus-tries forward through the next ten years. The technology is flexible enough to span computing platforms from servers to laptops to desktop PCs, and serve as the interconnect for Gigabit Ethernet, graph- ics, as well as numerous other generic I/O devices. This flexibility is afforded by PCI Express s layered architecture. The three architectural layers offer increased error detection and handling capabili-ties, flexible traffic prioritization and flow control policies, and the modularity to scale into the future. Additionally, PCI Express provides revolutionary capabilities for streaming media, hot plugging, and ad- vanced power manage-ment.
Image of page 290
Image of page 291

You've reached the end of your free preview.

Want to read all 300 pages?

  • Spring '16
  • PCI Express, adoption of PCI Express

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture