0e 4 cjsw180p probe v2 v3 v4 end 0s 10ns 20ns 30ns

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+CGSO=315P CGDO=315P CJ=2.0E-4 CJSW=180P .PROBE V(2) V(3) V(4) .END 0s 10ns 20ns 30ns 40ns 50ns Time 3.0V 2.0V 1.0V 0V v PC D 1 and D 2 The latch is perfectly balanced in Part (a) and the voltage levels remain symmetrical even after the PC transistor turns off. This would not happen in the real case because of small asymmetries and noise in the latch. Even a small capacitive imbalance will cause the latch to assume a preferred state. Try setting C BL2 = 425 fF in Part (a) for example. The asymmetry in the latch in Part (b) causes it to switch to a preferred state. 8.28 *PROBLEM 8.28 - Clocked NMOS Sense Amplifier VPC 2 0 DC 0 PULSE(3 0 1NS .5NS .5NS 250NS) VWL 6 0 DC 0 PULSE(0 3 2NS .5NS .5NS 250NS) VLC 9 0 DC 0 PULSE(0 3 3NS .5NS .5NS 250NS) VDD 3 0 DC 3 CBL1 5 0 2PF CBL2 4 0 2PF *Storage Cell MA1 5 6 1 0 MOSN W=2U L=2U AS=8P AD=8P CC 1 0 100FF *Dummy Cell MA2 4 6 7 0 MOSN W=2U L=2U AS=8P AD=8P CD 7 0 50FF *Sense Amplifier MPC 5 2 4 0 MOSN W=10U L=2U AS=40P AD=40P ML1 3 2 4 0 MOSN W=10U L=2U AS=40P AD=40P ML2 3 2 5 0 MOSN W=10U L=2U AS=40P AD=40P MS1 5 4 8 0 MOSN W=50U L=2U AS=200P AD=200P MS2 4 5 8 0 MOSN W=50U L=2U AS=200P AD=200P MLC 8 9 0 0 MOSN W=50U L=2U AS=200P AD=200P * .OP .TRAN 0.01NS 250NS .MODEL MOSN NMOS KP=5E-5 VTO=0.91 GAMMA=0.99
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8-264 +LAMBDA=.02 TOX=41.5N +CGSO=330P CGDO=330P CJ=3.9E-4 CJSW=510P .PROBE V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) V(9) .END 0s 50ns 100ns 125ns Time 3.0V 2.0V 1.0V 0V With only a 3 V power supply, the maximum bit-line differential is only 1.14 V which is achieved in 120 ns. (Relatively slow due to discharge of large bitline capacitance and relatively large threshold voltage of the NMOS transistors.) 8.29 *PROBLEM 8.29 - Clocked NMOS Sense Amplifier VPC 2 0 DC 0 PULSE(5 0 1NS .5NS .5NS 250NS) VWL 6 0 DC 0 PULSE(0 5 2NS .5NS .5NS 250NS) VLC 9 0 DC 0 PULSE(0 5 3NS .5NS .5NS 250NS) VDD 3 0 DC 5 CBL1 5 0 2PF CBL2 4 0 2PF *Storage Cell MA1 5 6 1 0 MOSN W=2U L=2U AS=8P AD=8P CC 1 0 100FF *Dummy Cell MA2 4 6 7 0 MOSN W=2U L=2U AS=8P AD=8P CD 7 0 50FF *Sense Amplifier MPC 5 2 4 0 MOSN W=10U L=2U AS=40P AD=40P ML1 3 2 4 0 MOSN W=10U L=2U AS=40P AD=40P ML2 3 2 5 0 MOSN W=10U L=2U AS=40P AD=40P MS1 5 4 8 0 MOSN W=50U L=2U AS=200P AD=200P MS2 4 5 8 0 MOSN W=50U L=2U AS=200P AD=200P MLC 8 9 0 0 MOSN W=50U L=2U AS=200P AD=200P * .OP .TRAN 0.01NS 250NS .MODEL MOSN NMOS KP=5E-5 VTO=0.91 GAMMA=0.99 +LAMBDA=.02 TOX=41.5N +CGSO=330P CGDO=330P CJ=3.9E-4 CJSW=510P .PROBE V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) V(9) .END
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8-265 0s 5ns 10ns 15ns 20ns 25ns 30ns Time 6.0V 4.0V 2.0V 0V With the 5 V power supply, the maximum bit-line differential is 1.75 V. A 1.5 V differential is achieved in approximately 15 ns, which is much faster than the 3 V case. 8.30 *PROBLEM 8.30 - Cascaded Inverter Pair VDD 1 0 DC 3 VI 2 0 DC 0 MN1 3 2 0 0 MOSN W=4U L=2U AS=16P AD=16P MP1 3 2 1 1 MOSP W=4U L=2U AS=16P AD=16P MN2 4 3 0 0 MOSN W=4U L=2U AS=16P AD=16P MP2 4 3 1 1 MOSP W=4U L=2U AS=16P AD=16P .OP .DC VI 0 3 0.001 .MODEL MOSN NMOS KP=5E-5 VTO=0.91 GAMMA=0.99 +LAMBDA=.02 TOX=41.5N +CGSO=330P CGDO=330P CJ=3.9E-4 CJSW=510P .MODEL MOSP PMOS KP=2E-5 VTO=-0.77 GAMMA=0.5 +LAMBDA=.05 TOX=41.5N +CGSO=315P CGDO=315P CJ=2.0E-4 CJSW=180P .PROBE V(2) V(3) V(4) .END
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