Immed or rt on “ 4” “sign” on 17 17 control

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Unformatted text preview: Immed OR Rt on “+4” “Sign” on 17 17 Control Signals for Control Signals for BEQ BEQ inst Register Transfer BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 ALUsrc = ? ALUctr = ? RegDst = ? RegWr=? nPC_sel = ? RegB SUB none off br 18 18 A Summary of A Summary of Control Signals Control Signals inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub” 19 19 A Summary of the Control A Summary of the Control Signals Signals add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr<2:0> 1 1 x Add 1 1 x Subtract 1 1 Or 1 1 1 1 Add x 1 x 1 1 Add x x 1 x Subtract x x x 1 x xxx op target address op rs rt rd shamt funct 6 11 16 21 26 31 op rs rt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 Appendix A 10 0000 See 10 0010 We Don’t Care :-) 20 20 The Concept of Local The Concept of Local Decoding Decoding R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop<N:0> 1 1 x “R-type” 1 1 Or 1 1 1 1 Add x 1 x 1 1 Add x x 1 x Subtract x x x 1 x xxx op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU 21 21 The Encoding of The Encoding of ALUop ALUop • In this exercise, ALUop has to be 2 bits wide to represent: In this exercise, ALUop has to be 2 bits wide to represent: – (1) “R-type” instructions (1) “R-type” instructions – “ “ I-type” instructions that require the ALU to perform: I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, and (4) Subtract (2) Or, (3) Add, and (4) Subtract • To implement the full MIPS ISA, ALUop has to be 3 bits to To implement the full MIPS ISA, ALUop has to be 3 bits to represent: represent: – (1) “R-type” instructions (1) “R-type” instructions – “ “ I-type” instructions that require the ALU to perform: I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)...
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