6 6 AREA vs SPEED \u00d8 When the designcompiler synthesizes your design it can

6 6 area vs speed ø when the designcompiler

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6) 6. AREA vs. SPEED Ø When the design_compiler synthesizes your design, it can attempt to minimize the 'area' of your design, and sacrifice speed. Or it can attempt to maximize the speed of your design by sacrificing area. Ø To ask the design_compiler to synthesize for area, from the menu choose: Attributes->Optimization Constraints->Design Constraints Set the 'maximum area' to 0. This will force the synthesizer to optimize for the smallest possible area: Ø If you wish the design compiler to optimize for speed, clear the max area field and press OK 7) Once you are finished specifying all of the design constraings, from the menu choose: Design Check Design, press OK
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Ø This step will check your design's netlist description for problems like connectivity, shorts, opens, multiple instantiations. If your design passes this step, in the “LOG” window, you should see no errors. 8) You are now ready to have the design_compiler synthesize your design using the AMI 0.5 standard cell library. Ø From the menu choose: Design Compile Design. You can ask the synthesizer to use 'low' 'medium' or 'high' effort to achieve the constraints you have set. The higher the effort, the longer the synthesize will take. If you design is large, this could mean several hours to days if you choose a 'high' effort. Ø For this exercise, 'medium' effort will be sufficient, that should be the default, press OK to being synthesis Part VI: Inspecting your Results 1) Once the synthesis is complete, you can view your 'synthesized' schematic. From the menu choose: Schematic New Design Schematic View Ø Your design will now be implemented using the AMI 0.5 standard cell library Ø You may double click on the 'half adders' to see what is inside each of them. You should see that they have been implemented using GATES from the standard cell library. Ø If you see components that don't map to a standardized cell, you may have done something in verilog that cannot be synthesized. You must investigate the cell and your verilog code to see what you have done incorrectly in verilog. 2) To view the critical path in your design, while in the schematic view, from the menu choose: Select Paths From/Through/to
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set the: delay type: max Ø The critical path will then be highlighted on the schematic window using a white line. Ø Alternatively, you can select Schematic Paths From/Through/to , and set the delay type to MAX . A new window will open up showing the entire critical path, gate by gate. 3. Checking if your constraints have been met. Ø If you have setup a clock that is FAR to fast for your design, the design_compiler will synthesize something, but it won't have met the constraint you have setup. Or if you set a fanin/fanout load that is unreasonable, the same will occur. You need to check the results of the synthesis by checking the synthesis reports.
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