4 bit universal register shift register 4 s 1 s 4 clk

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4-bit universal Register Shift Register 4 s 1 s 0 4 CLK Clear I_par A_par Function S 1 S 0 Register Operation 0 0 No change 0 1 Shift right 1 0 Shift left 1 1 Parallel Load Serial IN for Shift Right Serial IN for Shift Left
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C 4x1 mux D 0 1 2 s 1 s 0 C 4x1 mux D 0 1 2 s 1 s 0 C 4x1 mux D 0 1 2 s 1 s 0 C 4x1 mux D 0 1 2 s 1 s 0 Clear A 3 A 0 A 2 A 1 3 3 3 3 CLK I 3 I 2 I 1 I 0 Function S 1 S 0 Register Operation 0 0 No change 0 1 Shift right 1 0 Shift left 1 1 Parallel Load Serial IN for Shift Right Serial IN for Shift Left
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C D 0 1 2 C D 0 1 2 C D 0 1 2 C D 0 1 2 Clear A 3 A 0 A 2 A 1 3 3 3 3 CLK 0 0 0 0 0 0 0 0 The register maintains its state
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