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4. Logic Design (20 points) Answer 2 of parts A–D. If you change your mind, write “DISREGARD” on the question(s) you do not wish graded. Answer part E.A.(5 points) Draw diagrams showing how to implement AND, OR, and NOT gates using only NAND gates.B.(5 points) Draw a truth table for this circuit diagram.of 10172:4ABXYZ
C.(5 points) Write a sum-of-products formula for this truth table.D.(5 points) Simplify this formula using a K-map.ABCD00000010010101101000101111011110of 1117¯A¯B¯C¯D+¯AB¯C¯D+AB¯C¯D+AB¯CD+ABCD+ABC¯D+A¯BC¯D
E.(10 points) Design a finite-state machine that recognizes the sequence 1010, meaning it will output 1 if and only if the most recent four inputs were 1010. Indicate the number of states and the number of bits used to represent the state. Draw a state transition digram. For partial credit, show a truth table giving the output and next state. For full credit, also draw a circuit diagram for the truth table.of 1217
5. Caching (20 points) Consider a machine that uses 13-bit addresses. It has a direct-mapped cache with 8 sets using 4-byte blocks. The table below shows the metadata and content of the cache in hexadecimal.A.(5 points) Write:-The size of this cache, in bytes-The number of bits in the block offset-The number of bits in the set index-The number of bits in the tagB.(5 points) Assume (for this part only) we redesigned the cache to be 4-way associative, without changing the block size or cache size. Write:SetValidTag012301103030133710000000000020FFFFFF01DC31351F2EFADE4118060000005000000000006119A22B950071A70000000017