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**Unformatted text preview: **= switching activity rate – Switched capacitance – C EFF = C L x α 1 – Power dissipation is data dependent (switching probability) • Activity over N cycles Examples of transition probabilities: NOR vs XOR Assume Signal Probabilities p A=1 = ½ p B=1 = ½ Transition Probability p 1 = p out=0 x p out=1 = ¾ x ¼ = 3/16 C EFF =3/16 x C L Static 2-input NOR gate Static 2-input XOR gate Assume Signal Probabilities p A=1 = ½ p B=1 = ½ Transition Probability p 1 = p out=0 x p out=1 = 1/2 x 1/2 = 1/4 C EFF =1/4 x C L 5 Short Circuit Current • When transistors switch, both nMOS and pMOS networks may be momentarily ON at once • Leads to a blip of “short circuit” current. • Keep input/output rise/fall times the same – <20% of dynamic power dissipation Large capacitive load VDD Vout CL Vin ISC Small capacitive load VDD Vout CL Vin ISC IMAX C L =0 C L = ∞ Increasing C L time Short-circuit current Input rise time Dynamic Example • 200 Mtransistor chip – 20M logic transistors: Average width: 12 – 180M memory transistors: Average width: 4 – 1.2 V 100 nm process, C g = 2 fF/ m – Static CMOS logic gates: activity factor = 0.1 – Memory arrays: activity factor = 0.05 (many banks!) • Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current. 6 logic 6 mem 2 dynamic logic mem 20 10 12 0.05 / 2 / 24 180 10 4 0.05 / 2 / 72 0.1 0.05 1.2 8.6 mW/MHz C m f F m n F C m f F m n F P C C f 6 Static Power • Static power is consumed even when chip is quiescent. – Example: Pseudo nMOS logic • P static = p 1 V DD I DC (not a function of switching frequency) – Assume prob. of “1” (p 1 ) is 50% f inputs Y Inverter NAND2 NOR2 4/3 2/3 A Y 8/3 8/3 2/3 B A Y A B 4/3 4/3 2/3 Y A=HI Y I DC Leakage Sources • Subthreshold conduction – Transistors can’t abruptly turn ON or OFF • Junction leakage...

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- Fall '09
- Guan
- Logic gate, Vdd, leakage, subthreshold leakage