There is a relatively large and slow main memory together with a smaller faster

There is a relatively large and slow main memory

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There is a relatively large and slow main memory together with a smaller, faster cache memory. The cache contains a copy of portions of main memory 26
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When the processor attempts to read a word of memory, a check is made to determine if the word is in the cache. If so, the word is delivered to the processor. If not, a block of main memory, consisting of some fixed number of words, is read into the cache and then the word is delivered to the processor 27
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ELEMENTS OF CACHE DESIGN Cache Address Cache Size Map Function Number of Caches 28
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Cache Addresses: Logical Vs Physical Address?? 29 Stores data using virtual addresses. Advantage: cache access speed is faster, cache can respond before the MMU performs an address translation
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Disadvantage: each application sees a virtual memory that starts at address 0. Thus, the same virtual address in two different applications refers to two different physical addresses Solution flushed with each application context switch, or extra bits must be added to each line of the cache to identify which virtual address space this address refers to. 30
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A physical cache stores data using main memory physical addresses. 31
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Cache Size Dilemma Small enough so that the overall average cost per bit is close to that of main memory alone and large enough so that the overall average access time is clo se to that of the cache alone Motivations for minimizing cache size The larger the cache, the larger the number of gates involved in addressing the cache. tend to be slightly slower than small ones . 32
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Processo r Type Year of Introdu ction L1 Cache L2 Cache L3 Cache Intel 80486 PC 1989 8 kB - - IBM 360/85 Mainframe 1968 16 to 32 kB - - PowerPC G4 PC/server 1999 32 kB/32 kB 256 KBto 1 MB 2 MB Pentium 4 PC/server 2000 8 kB/8 kB 256 KB - 33
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Mapping Function Challenges??? fewer cache lines than main memory blocks determining which main memory block currently occupies a cache line The choice of the mapping function dictates how the cache is organized direct associative set associative 34
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Direct Mapping 35
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Direct Mapping To see how the direct mapping organization operated ,consider the numerical example shown below. The word at address zero is presently stored in the cache (index=000, tag=00,data=1220).suppose that the cpu now wants to access the word at address 02000. the index address is 000, so it is used to access the cache. The two tags are then compared . The cache tag is 00 but the address tag is 02, which does not produce a match. Therefore , the main memory is accessed a 02 nd data word 5670 is transferred to the cpu. The cache word at index address 000 is then replaced with a tag of and data of 5670.
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  • Fall '19
  • Central processing unit, CPU cache

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