Memory 1 a 1 invalidate protocol basic idea maintain

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Memory 1 A 1 Invalidate Protocol Basic idea: maintain single writer property Only one processor has write permission at any point in time Write handling On write, invalidate all other copies of data Make data private to the writer Allow writes to occur until data is requested Supply modified data to requestor directly or through memory Minimal set of states per cache line: Invalid (not present) Modified (private to this cache) State transitions: Local read or write: I >M, fetch modified Remote read or write: M >I, transmit data (directly or through memory) Writeback: M >I, write data to memory Invalidate Protocol Optimizations Observation: data can be read shared Add S (shared) state to protocol: MSI State transitions: Local read: I >S, fetch shared Local write: I >M, fetch modified; S >M, invalidate other copies Remote read: M >S, supply data Remote write: M >I, supply data; S >I, invalidate local copy Observation: data can be write private (e.g. stack frame) Avoid invalidate messages in that case Add E (exclusive) state to protocol: MESI State transitions: Local read: I >E if only copy, I >S if other copies exist Local write: E >M silently, S >M, invalidate other copies Sample Invalidate Protocol (MESI) M BR LW EV or BW LW I S E EV or BW or BU LR/S LR/~S LW EV or BW BR Sample Invalidate Protocol (MESI) Current State s Event and Local Coherence Controller Responses and Actions (s' refers to next state) Local Read (LR) Local Write (LW) Local Eviction (EV) Bus Read (BR) Bus Write (BW) Bus Upgrade (BU) Invalid (I) Issue bus read if no sharers then s ' = E else s ' = S Issue bus write s ' = M s ' = I Do nothing Do nothing Do nothing Shared (S) Do nothing Issue bus upgrade s ' = M s ' = I Respond shared s ' = I s ' = I Exclusive (E) Do nothing s ' = M s ' = I Respond shared s ' = S s ' = I Error Modified (M) Do nothing Do nothing Write data back; s ' = I Respond dirty; Write data back; s ' = S Respond dirty; Write data back; s ' = I Error
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