Beq jump regwrite 1 1 1 op 00 10 00

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Unformatted text preview: beq jump RegWrite 1 1 1 op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 • RegWrite = R-type + ori + lw RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw) (lw) op<0> op<5> . . op<5> . . <0> op<5> . . <0> op<5> . . <0> op<5> . . <0> op<5> . . <0> R-type ori lw sw beq jump RegWrite 33 33 PLA Implementation of the Main PLA Implementation of the Main Control Control op<0> op<5> . . op<5> . . <0> op<5> . . <0> op<5> . . <0> op<5> . . <0> op<5> . . <0> R-type ori lw sw beq jump RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop<2> ALUop<1> ALUop<0> 34 34 Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle Processor Processor 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr<5:0> Instr<31:26> Instr<15:0> nPC_sel 35 35 Drawback of this Single Cycle Drawback of this Single Cycle Processor Processor • Long cycle time: Long cycle time: – Cycle time must be long enough for the load Cycle time must be long enough for the load instruction: instruction: PC’s Clock -to-Q + PC’s Clock -to-Q + Instruction Memory Access Time + Instruction Memory Access Time + Register File Access Time + Register File Access Time + ALU Delay (address calculation) + ALU Delay (address calculation) + Data Memory Access Time + Data Memory Access Time + Register File Setup Time + Register File Setup Time + Clock Skew Clock Skew...
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  • Fall '05
  • WeiChungHsu
  • Trigraph, Rw Ra Rb, Datapath Inst Memory, 32-bit Registers busB

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