# 46 repeat problem 45 for the circuit shown in fig 773

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46. Repeat Problem 45 for the circuit shown in Fig. 7.73. 47. Assuming , calculate the voltage gain of the circuit shown in Fig. 7.74. Explain why this stage is not a common-gate amplifier.

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 365 (1) Sec. 7.6 Chapter Summary 365 V R DD D out V M 1 I 1 C 1 in V = 1.8 V Figure 7.70 V DD out V M 1 V b in V R S M 2 V DD out V M 1 V b in V M 2 R D V DD out V M 1 V b in V R S M 2 R 1 V DD out V M 1 V b in V M 2 M V b 3 R D out V M M in V V b 1 R D I 1 V DD 2 (c) (a) (b) (d) (e) Figure 7.71 48. Calculate the voltage gain of the stage depicted in Fig. 7.75. Assume and the capaci- tors are very large. 49. The source follower shown in Fig. 7.76 is biased through . Calculate the voltage gain if and . 50. We wish to design the source follower shown in Fig. 7.77 for a voltage gain of 0.8. If and , determine the required gate bias voltage. 51. The source follower of Fig. 7.77 is to be designed with a maximum bias gate voltage of 1.8 V. Compute the required value of for a voltage gain of 0.8 if . 52. The source follower depicted in Fig. 7.78 employs a current source. Determine the values of and if the circuit must provide an output impedance less than 100 with V. Assume . 53. The circuit of Fig. 7.78 must exhibit an output impedance of less than 50 with a power budget of 2 mW. Determine the required value of . Assume .
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 366 (1) 366 Chap. 7 CMOS Amplifiers V R DD out V M V b in V M 1 R D1 D2 X 2 Figure 7.72 V R DD out V M V b in V D2 X R D1 M 1 2 Figure 7.73 V DD out V M 1 in V I 1 R G Figure 7.74 54. We wish to design the source follower of Fig. 7.79 for a voltage gain of 0.8 with a power budget of 3 mW. Compute the required value of . Assume is very large and . 55. Determine the voltage gain of the stages shown in Fig. 7.80. Assume . 56. Consider the circuit shown in Fig. 7.81, where a source follower ( and ) precedes a common-gate stage ( and ). (a) Writing , compute the overall voltage gain. (b) Simplify the result obtained in (a) if . Design Problems In the following problems, unless otherwise stated, assume . 57. Design the CS stage shown in Fig. 7.82 for a voltage gain of 5 and an output impedance of 1 k . Bias the transistor so that it operates 100 mV away from the triode region. Assume the capacitors are very large and . 58. The CS amplifier of Fig. 7.82 must be designed for a voltage gain of 5 with a power budget of 2 mW. If V, determine the required value of . Make the same assumptions

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 367 (1) Sec. 7.6 Chapter Summary 367 V DD out V M 1 R R D R 1 C B R R 2 3 4 in V C 1 Figure 7.75 M 1 V DD R in V G R S out V 1 k 50 k = 1.8 V Figure 7.76 M 1 V DD in V R S out V 500 = 1.8 V Figure 7.77 M 1 V DD out V in V I 1 = 1.8 V Figure 7.78 as those in Problem 57. 59. We wish to design the CS stage of Fig. 7.82 for maximum voltage gain but with and a maximum output impedance of 500 . Determine the required current. Make the same assumptions as those in Problem 57.
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