It is possible that prior to the completion of the

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It is possible that prior to the completion of the pending write, another instruction can come along and also has that same register as its destination register. If this occurs, the operands (or pseudo operands) needed by this instruction are still copied to an available reservation station. In addition, the tag field of the destination register of this instruction is updated with the ID of this new reservation station, i.e. the old tag value is overwritten. This will ensure that the said register will get the latest value, i.e. the late completing earlier write cannot overwrite a later write. Hence, the output dependence is resolved without stalling a physical functional unit, not requiring additional buffers to ensure sequential write back to the register file.
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© 2005 Mikko Lipasti Example 3 Cycle #1 DISPATCHED INSTRUCTION(S): i, j ID Tag Sink Tag Source ID Tag Sink Tag Source Busy Tag Data j 1 0 6.0 4 i 4 0 6.0 0 7.8 0 6.0 2 5 2 x 1 3.5 3 Mult/Div i 4 x 4 10.0 Adder 8 7.8 Cycle #2 DISPATCHED INSTRUCTION(S): k, l ID Tag Sink Tag Source ID Tag Sink Tag Source Busy Tag Data j 1 0 6.0 4 i 4 0 6.0 0 7.8 0 6.0 k 2 0 6.0 0 7.8 l 5 2 0 7.8 2 x 1 3.5 3 Mult/Div i 4 x 2 10.0 Adder k 8 x 5 7.8 i: R4 <= R0 * R8 j: R2 <= R0 + R4 (RAW on R4) k: R4 <= R0 + R8 (WAW on R4) l: R8 <= R4 * R8 (RAW on R4) Cycle #3 DISPATCHED INSTRUCTION(S): ID Tag Sink Tag Source ID Tag Sink Tag Source Busy Tag Data j 1 0 6.0 4 i 4 0 6.0 0 7.8 0 6.0 k 2 0 6.0 0 7.8 l 5 2 0 7.8 2 x 1 3.5 3 Mult/Div i 4 x 2 Adder k 8 7.8 What if j causes FP overflow exception? - where is R4? - it is lost => imprecise exceptions! 13.8
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Summary of Tomasulo’s Algorithm Supports out of order execution of instructions. Resolves dependences dynamically using hardware. Attempts to delay the resolution of dependencies as late as possible. Structural dependence does not stall issuing; virtual FU’s in the form of reservation stations are used. Output dependence does not stall issuing; copying of old tag to reservation station and updating of tag field of the register with pending write with the new tag. True dependence with a pending write operand does not stall the reading of operands; pseudo operand (tag) is copied to reservation station. Anti-dependence does not stall write back; earlier copying of operand awaiting read to the reservation station. Can support sequence of multiple output dependences. Forwarding from FU’s to reservation stations bypasses the register file.
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Tomasulo vs. Modern OOO IBM 360/91 Modern Width Peak IPC = 1 4+ Structural hazards 2 FPU Single CDB Many FU Many busses Anti-dependences Operand copy Reg. Renaming Output dependences Renamed reg. tag Reg. renaming True dependences Tag-based forw. Tag-based forw. Exceptions Imprecise Precise (ROB) Implementation 3 x 66” x 15” x 78” 60ns cycle time 11-12 gate delays per pipe stage >$1 million 1 chip 300ps < $100
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Example 4 i: R4 <-- R0 + R8 j: R2 <-- R0 * R4 k: R4 <-- R4 + R8 l: R8 <-- R4 * R2
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Example 4 (2) (3) (2) (3) (10) (2) (3) (2) (3) (8) i j k l i j k l Can Tomasulo’s algorithm reach dataflow limit of 8?
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Example 4 Adder Tag Sink Tag Source Mult/Div Tag Sink Tag Source BusyTag Data ID ID 2 3 1 4 5 DISPATCHED INSTRUCTION(S): ______________ 6.0 0 2 4 8 3.5 10.0 7.8 CYCLE #1 CYCLE #2 Adder Tag Sink Tag Source Mult/Div Tag Sink Tag Source BusyTag Data ID ID 2 3 1 4 5 DISPATCHED INSTRUCTION(S): ______________ 0 2 4 8 CYCLE #3 Adder Tag Sink Tag Source Mult/Div Tag Sink Tag Source BusyTag Data ID ID 2 3 1 4 5 DISPATCHED INSTRUCTION(S): ______________ 0 2 4 8
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Example 4 CYCLE #4 CYCLE #5 Adder Tag
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  • Fall '09
  • PROFGURISOHI
  • Processor register, Register renaming, Tomasulo algorithm, Register file, Out-of-order execution

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