10 1 10 Gate Level Optimizations 10 During gate level optimizations Design

# 10 1 10 gate level optimizations 10 during gate level

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10-110Gate-Level Optimizations10During gate-level optimizations, Design Compiler implements the final netlist by making optimal selections of library cells. It performs tasks such as delay optimization, design rule fixing, and area recovery. Design Compiler’s optimization algorithms use costs to determine if a design change is an improvement. Design Compiler calculates two cost functions: one for design rule constraints and one for optimization constraints and accepts an optimization move if it decreases the cost of one component without increasing more-important costs. Before you read this chapter, read the “Optimization Flow” on page 1-9 to understand how gate-level optimizations fit into the overall compile flow.This chapter contains the following sections:Compile Cost FunctionChanging the Cost FunctionCompile LogDelay OptimizationDesign Rule FixingArea Recovery
10-2Chapter 10: Gate-Level OptimizationsCompile Cost FunctionDuring gate-level optimization, Design Compiler calculates two cost functions: one for design rule constraints and one for optimization constraints. Cost calculations are affected by constraints such as user-specified constraints (for example, create_clock), library constraints (for example, max_fanout), and built-in optimization goals (for example, area cleanup). A cost function consists of deltas from these constraints, that is, the positive difference between the actual value and target value of the constraint. When evaluating cost function components, Design Compiler considers these violators and works to reduce the cost function to zero.Design Compiler reports the value of each cost function whenever a change is made to the design. The compile cost function considers only those components that are active in your design. Design Compiler evaluates each cost function component independently, in order of importance.Design Compiler evaluates cost function components independently in order of importance and accepts an optimization move if it decreases the cost of one component without increasing more-important costs. For example, an optimization move that improves maximum delay cost is always accepted. Optimization stops when all costs are zero or no further improvements can be made to the cost function.Design Rules Cost FunctionDesign rule constraints reflect technology-specific restrictions your design must meet in order to function as intended. The design rules cost function has the components shown in Figure 10-1. Figure 10-1Design Rules Cost FunctionThe design rules cost function takes into account the following design rule constraints:Maximum transition timeMaximum fanoutMaximum capacitanceΣ∆max_fanout+ Σ∆max_transition + Σ∆max_capacitanceCost =
10-3Compile Cost FunctionCalculating Transition Time CostThe maximum transition time for a net is the longest time required for its driving pin to change logic values. Design Compiler determines driver transition times from the technology library.