x y Fx OR y Fx NOR y 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 Figure 63 Truth table for

X y fx or y fx nor y 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1

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x y F=x OR y F=x NOR y 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 Figure 6.3 Truth table for OR and NOR gates c. AND & NAND Gates AND gate takes two or more inputs and produces an output of 1 if and only if all the inputs are 1 , otherwise it gives 0 outputs. On the other hand, NAND gate produces an output of 0 for only when all the inputs are 1 . The logic symbol for two-input AND & NAND gates is drawn in fig. 6.4. x y F x y F (a) AND Gate Symbol (b) NAND Gate Symbo Figure 6.4 Logic symbols for OR & NOR gates Truth table for AND & NAND Gate is shown in the table below
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Applied Electronic II Adama University EENG 2202 3 Electrical Engineering x y F=x AND y F=x NAND y 1 1 1 0 1 0 0 1 0 1 0 1 0 0 0 1 Figure 6.5 Truth table for AND & NAND gate d. XOR and XNOR Gates XOR (exclusive OR) logic gate is a special class of derived logic gate that produce an output of 1 , only when one of the inputs is 1 . XNOR does the opposite of XOR which outputs 0 when one of the inputs is 1. The logic symbol for XOR and XNOR gates is shown in figure 6.6. X Y X Y (a) XOR gate (b) XNOR gate F F Figure 6.6 Logic symbol for XOR and XNOR gates Truth table of XOR and XNOR gates for two inputs is given in the following table. x y F=x XOR y F=x XNOR y 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0 1 Figure 6.7 Truth table of two-input XOR and XNOR gates 6.2 REALIZATION OF DISCREET LOGIC GATES Visualization of Gates with Binary switches Two binary switches can be connected together either in series or in parallel to develop AND & OR gate operations respectively.
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Applied Electronic II Adama University EENG 2202 4 Electrical Engineering + - X Y F R +5V + - X Y F R +5V (a) (b) . Figure 6.8 Switch realizations of gates If two switches are connected in series as in figure 6.8 (a), then both switches have to be on in order for the output F to be a 1 . In other words, F = 1 if x = 1 and y = 1. If either x or y is off, or both are off, then F = 0. This can be translated into the AND gate operation. If we connect two switches in parallel as in figure 6.8 (b), then only one switch needs to be on in order for the output F to be a 1 . In other words, F = 1 if either x = 1, or y = 1, or both x and y are 1’s. This means that F = 0 only if both x and y are 0 ’s. This is similar to the operation of OR gate. Realization of Gates with Digital Integrated Circuit Physical circuits deal with physical properties, such as voltages and currents. Digital circuits use the abstractions of 0 and 1 to represent the presence or absence of these physical properties. In fact, a range of voltages is interpreted as the logic 0 , and another, non-overlapping range is interpreted as the logic 1 . These ranges vary for different logic families. Traditionally, digital circuits operate with a 5-volt power supply. In such a case, it is customary to interpret the voltages in the range 0– 1.5 V as logic 0 , while voltages in the range 3.5–5 V as logic 1 . This is shown in Figure 6.9. Voltages in the middle range (from 1.5–3.5 V) are undefined and should not occur in the circuit except during transitions from one state to the other. However, they may be interpreted as a “weak” logic 0 or a “weak” logic 1.
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