Be above that of the cpu by setting the appropriate

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be above that of the CPU by setting the appropriate bits in the EDS Bus Master Priority Control (MSTRPR) register. All bus masters with raised priorities will maintain the same priority relationship relative to each other (i.e., M1 being highest and M3 being lowest, with M2 in between). Also, all the bus masters with priorities below that of the CPU maintain the same priority relationship relative to each other. The priority schemes for bus masters with different MSTRPR values are listed in Table 4-44 . Figure 4-13 shows the arbiter architecture. The bus master priority control allows the user application to manipulate the real-time response of the system, either statically during initialization or dynamically in response to real-time events. TABLE 4-44: DATA MEMORY BUS ARBITER PRIORITY FIGURE 4-13: ARBITER ARCHITECTURE Priority MSTRPR<15:0> Bit Setting ( 1 ) 0x0000 0x0020 M0 (highest) CPU DMA M1 Reserved CPU M2 Reserved Reserved M3 DMA Reserved M4 (lowest) MPLAB ® ICD MPLAB ICD Note 1: All other values of MSTRPR<15:0> are reserved. MPLAB ® ICD Reserved Data Memory Arbiter M0 M1 M2 M3 M4 MSTRPR<15:0> DMA CPU SRAM
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dsPIC33EVXXXGM00X/10X FAMILY DS70005144E-page 74 2013-2016 Microchip Technology Inc. 4.3.4 SOFTWARE STACK The W15 register serves as a dedicated Software Stack Pointer (SSP) and is automatically modified by exception processing, subroutine calls and returns; however, W15 can be referenced by any instruction in the same manner as all other W registers. This simpli- fies reading, writing and manipulating the SSP (for example, creating stack frames). W15 is initialized to 0x1000 during all Resets. This address ensures that the SSP points to valid RAM in all dsPIC33EVXXXGM00X/10X family devices and per- mits stack availability for non-maskable trap exceptions. These can occur before the SSP is initialized by the user software. You can reprogram the SSP during initialization to any location within the Data Space. The SSP always points to the first available free word and fills the software stack, working from lower toward higher addresses. Figure 4-14 illustrates how it pre- decrements for a stack pop (read) and post-increments for a stack push (writes). When the PC is pushed onto the stack, PC<15:0> are pushed onto the first available stack word, then PC<22:16> are pushed into the second available stack location. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, as shown in Figure 4-14 . During exception processing, the MSB of the PC is concatenated with the lower 8 bits of the CPU STATUS Register (SR). This allows the contents of SRL to be preserved automatically during interrupt processing. FIGURE 4-14: CALL STACK FRAME 4.4 Instruction Addressing Modes The addressing modes shown in Table 4-45 form the basis of the addressing modes optimized to support the specific features of the individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types.
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