# 1 q q r s hold state s r q q state 1 1 set 0 1 0 1

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Q Q R S HOLD State 0 0 S R Q Q State 1 0 1 0 SET 0 1 0 1 RESET 0 0 HOLD 1 0 Q Q 1 1 0 0 INVALID S R Q Q State 1 0 1 0 SET 0 0 1 0 HOLD 0 1 0 1 RESET 0 0 HOLD 0 1 1 bit memory? 1 0
Q Q R S 1 1 0 0 Both the outputs are well defined and 0. The first problem is that we do not get complementary output.

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Q Q R S 1 1 0 0 Both the outputs are well defined and 0. The first problem is that we do not get complementary output. A more serious problem occurs when we switch the latch to the hold state by changing RS from 11 00 . Suppose the inputs do not change simultaneously and we get the situation 11 01 * 00 Q Q R S Q Q R S Q Q R S 1 1 0 0 0 1 1 0 0 0 1 0 Q = 1
Q Q R S Q Q R S Q Q R S 1 1 0 0 0 1 1 0 0 0 1 0 Q = 1

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Q Q R S Q Q R S Q Q R S 1 1 0 0 0 1 1 0 0 0 1 0 Q = 1 Suppose the inputs change as RS = 11 10* 00
Q Q R S Q Q R S Q Q R S 1 1 0 0 0 1 1 0 0 0 1 0 Q = 1 Q Q R S Q Q R S Q Q R S 1 1 0 0 1 0 0 1 0 0 0 1 Q = 0 Suppose the inputs change as RS = 11 10* 00

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Q Q R S Q Q R S Q Q R S 1 1 0 0 0 1 1 0 0 0 1 0 Q = 1 Q Q R S Q Q R S Q Q R S 1 1 0 0 1 0 0 1 0 0 0 1 Q = 0 Suppose the inputs change as RS = 11 10* 00 So although output is well defined when we apply RS = 11, it becomes unpredictable once we switch the latch to hold state by applying RS = 00. That is why RS = 11 is not used as an input combination.
NAND Latch Q Q R S S R Q Q State 0 1 1 0 SET 1 0 0 1 RESET 1 1 HOLD Q Q 0 0 1 1 INVALID

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