Differential Signaling 1 OV Reference or some common mode DC voltage D 1

Differential signaling 1 ov reference or some common

This preview shows page 147 - 149 out of 300 pages.

cal bit is determined by the direction in which the signals swing. Differential Signaling 0 1 0 OV Reference or some common mode DC voltage D+ 0 1 0 Parallel Multi- Drop Signaling OV Reference D- Figure 8.8 Signaling Comparison
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148 Introduction to PCI Express: A Hardware and Software Developers Guide There are several advantages that differential signaling offers over conventional parallel multi-drop bus signaling. A comparison of a differ- ential pair to a parallel multi-drop bus signal illustrates these advantages. Assume that a parallel multi-drop bus signal swings from 0 volts to +1 volt to represent logical bits electrically. Also consider the differential pair mentioned above, which swings the positively notated signal and the negatively notated signal to +/-1 volt. The parallel multi-drop buffer swings the line to 1 volt, consequently sending the electrical equivalence of the logical bit 1 down the bus. As the signal travels it becomes attenu- ated before it reaches the receive buffers on the other side. For now, as- sume that the receive buffers have been designed sensitive enough to detect the signal after it has been attenuated to some extent. Next sup- pose that the line is held at 0 volts to transmit the logical bit 0 down the bus. At the transmit side the buffer holds the line at 0 volts. However, at some point along the bus some noise couples onto the line and propa- gates down to the receiving device. To counteract signal attenuation, the receive buffers have been designed to be very sensitive to detect bus transitions. Unfortunately, the noise that has coupled onto the bus is large enough in magnitude to register a logical 1 transition at the receive side even though the transmit buffers were holding the bus low. The end result is data corruption. This is the big problem with parallel multi-drop bus design. The challenge is to have receive buffers with sensitivity suit- able to register electrical transitions yet somewhat immune to noise. Now take the case of the differential buffers sending the same bits down the bus as was done in the parallel multi-drop case. To send a logi- cal 1 bit down the bus, the positively notated line swings to +1 volt and the negatively notated bit swings to 1 volt. As the signal travels it be- comes attenuated before it reaches the receive buffers on the other side. If the signal were to be attenuated by 50 percent the relative difference between the positively notated line and the negatively notated line would still be 1 volt. The receive buffers need not be nearly as sensitive in de- sign as the parallel multi-drop case. Now consider the case that the logi- cal bit 0 is transferred down the bus. For the differential bus the positively and negatively notated lines swing to the opposite voltage sig- nifying a switch in bit polarity. Also consider that the same noise source that coupled onto the parallel multi-drop line couples onto the differen- tial pair. Since the differential receiver measures the relative difference between the differential pair, any noise that gets coupled onto the pair is inconsequential. Differential signaling allows designers to deal with plat-
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