What are gate primitives Verilog supports basic logic gates as predefined

What are gate primitives verilog supports basic logic

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51. What are gate primitives? 52. Give the two blocks in behavioral modeling. 53. What are the types of conditional statements? 1. No else statement Syntax : if ( [expression] ) true statement; 2. One else statement Syntax : if ( [expression] ) true statement; else false-statement; 3. Nested if-else-if Syntax : if ( [expression1] ) true statement 1; else if ( [expression2] ) true-statement 2; else if ( [expression3] ) true-statement 3; else default-statement; The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed. 54. Name the types of ports in Verilog 55. What are the types of procedural assignments? 56. Give the different symbols for transmission gate. 57. Give the different types of ASIC. 1. Full custom ASICs 2. Semi-custom ASICs * standard cell based ASICs * gate-array based ASICs 3. Programmable ASICs * Programmable Logic Device (PLD) * Field Programmable Gate Array (FPGA). 58. What is the full custom ASIC design? 59. What is the standard cell-based ASIC design? 61. Give the constituent of I/O cell in 22V10. * 10 I/Os * product time 9 10 12 14 16 14 12 10 8 * 24 pins 62. What is a FPGA?

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