Figure 6 The distribution of the inter device HD of Device 1 under the active

Figure 6 the distribution of the inter device hd of

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Figure 6. The distribution of the inter-device HD of Device 1 under the active clock duration is 4. Figure 7. The distribution of the inter-device HD of Device 1 under the active clock duration is 8. Figure 8. The distribution of the inter-device HD of Device 1 under the active clock duration is 16. R EFERENCES [1] P. C. Kocher, “Timing attacks on implementations of diffie-hellman, RSA, DSS, and other systems,” in CRYPTO’96 , 1996, pp. 104–113. [2] P. Kocher, J. Jaffe, and B. Jun, “Differential power analysis,” in CRYPTO’99 , 1999, pp. 388–397. [3] A. Moradi, A. Barenghi, T. Kasper, and C. Parr, “On the vulnerability of FPGA bitstream encryption against power analysis attacks—extracting keys from Xilinx Virtex-II FPGAs,” Cryptology ePrint Archive, 2011. [4] A. Moradi, M. Kasper, and C. Paar, “On the portability of side-channel attacks –an analysis of the Xilinx Virtex 4 and Virtex 5 bitstream encryption mechanism,” Cryptology ePrint Archive, 2011. [5] S. R. Pappu, “Physical one-way functions,” Ph.D. dis- sertation, MIT, 2001. [6] R. Maes and I. Verbauwhede, “Physically unclonable functions: A study on the state of the art and future re- search directions,” in Towards Hardware-Intrinsic Se- curity , A.-R. Sadeghi and D. Naccache, Eds. Springer- Verlag, 2010, ch. 1, pp. 3–37. [7] D. Lim, J. W. Lee, B. Gassend, G. E. Suh, M. van Dijk, and S. Devadas, “Extracting secret keys from integrated circuits,” IEEE Trans. VLSI Syst. , vol. 13, no. 10, pp. 1200–1205, 2005. [8] G. E. Suh and S. Devadas, “Physical physical unclon- able functions for device authentication and secret key generation,” in DAC’07 , 2007, pp. 9–14. [9] D. Suzuki and K. Shimizu, “The glitch PUF: A new delay-PUF architecture exploiting glitch shapes,” in Proc. CHES2010 , 2010, pp. 366–382. [10] J. Guajardo, S. S. Kumar, G.-J. Schrijen, and P. Tuyls, “FPGA intrinsic PUFs and their use for IP protection,” in CHES’07 , 2007, pp. 63–80. [11] S. S. Kumar, J. Guajardo, R. Maesyz, G.-J. Schrijen, and P. Tuyls, “The butterfly PUF,” in HOST’08 , 2008, pp. 67–70. [12] E. Ozturk, G. Hammouri, and B. Sunar, “Physical unclonable function with tristate buffers,” in ISCAS’08 , 2008, pp. 3194–3197. [13] M. George and P. Alfke, “Linear feedback shift registers in Virtex devices,” Xilinx apprication note XAPP210, 2007. [14] S. Akashi, K. Toshihiro, and S. Hirofumi, “Secure im- plementation of cryptographic modules—development of a standard evaluation environment for side channel attacks,” Synthesiology , vol. 3, no. 1, pp. 56–65, 2010. [15] Y. Hori, T. Yoshida, T. Katashita, and A. Satoh, “Quan- titative and statistical performance evaluation of arbiter physical unclonable functions on FPGAs,” in Proc. ReConFig2010 , 2010, pp. 298–303. 228
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