Sushma rawal 31 based on register size processors can

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SUSHMA RAWAL 31 Based on register size Processors can be classified as 8 bit/16 bit/32 bit /64 bit based on the size of their internal registers. Typically, the data bus width equals the size of the data registers so that the register data can be read/written in one read/write cycle.
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SUSHMA RAWAL 32 Based on Endianness Big Endian Eg: SPARC, power PC Little Endian Intel processors Configurable Processors some processors can be configured during bootup process as big or little endian. Eg: ARM processors
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SUSHMA RAWAL 33 Based on Instruction Set RISC Only load/store instructions use the external memory. All instructions are same size and fixed length. Number of instructions available are less compared to CISC. Typically has less pipeline stages than CISC. Eg ARM processor.
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SUSHMA RAWAL 34 Based on Instruction set CISC Most instructions can operation directly on external memory. Hence require less number of registers. Instructions are of different sizes. Hence they take varied clock cycle to decode and execute each instruction Pipeline stages take varied times and hence pipeline is not so efficient as the RISC processors.
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SUSHMA RAWAL 35 Based on Instruction set CISC More number of instructions since many complex operations are implemented Eg: Intel Pentium processors
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SUSHMA RAWAL 36 Based on Bus Architecture-Von Neumann A Von-Neumann Machine Architecture provides one data path (bus) for both instruction and data As a result, the CPU can either be fetching an instruction from memory, or read/writing data to it Other than less complexity of hardware, it allows for using a single, sequential memory. Today’s processing speeds vastly outpace memory access times, and we employ a very fast but small amount of memory (cache) local to the processor
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SUSHMA RAWAL 37 Based on Bus Architecture- Harvard Harvard Architecture refers to a memory structure where the processor is connected to two different memory banks via two sets of buses This is to provide the processor with two distinct data paths, one for instruction and one for data Through this scheme, the CPU can read both an instruction and data from the respective memory banks at the same time This inherent independence increases the throughput of the machine by enabling it to always prefetch the next instruction The cost of such a system is complexity in hardware Commonly used in DSPs
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SUSHMA RAWAL 38 Based on Bus Architecture Modern processors employ a Harvard Architecture to read from two instruction and data caches, when at the same time using a Von-Neumann Architecture to access external memory
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SUSHMA RAWAL 39 Based on Functionality General purpose processors: - All the regular processors Special purpose processors: - Digital Signal Processors DSP processors are microprocessors designed for efficient mathematical manipulation of digital signals.
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