# 333 m 1 v dd a m 2 in v out v in v v cc out v q 1 q 2

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333 M 1 V DD (a) M 2 in V out V in V V CC out V Q 1 Q 2 M 1 in out v v g 1 m2 r O2 r O1 (c) (b) Figure 7.12 (a) MOS stage using a diode-connected load, (b) bipolar counterpart, (c) simplified circuit of (a). (7.55) (7.56) (7.57) Interestingly, the gain is given by the dimensions of and and remains independent of process parameters and and the drain current, . The reader may wonder why we did not consider a common-emitter stage with a diode- connected load in Chapter 5. Shown in Fig. 7.12(b), such a circuit is not used because it provides a voltage gain of only unity: (7.58) (7.59) (7.60) The contrast between (7.57) and (7.60) arises from a fundamental difference between MOS and bipolar devices: transconductance of the former depends on device dimensions whereas that of the latter does not. A more accurate expression for the gain of the stage in Fig. 7.12(a) must take channel-length modulation into account. As depicted in Fig. 7.12(c), the resistance seen at the drain is now equal to , and hence (7.61) Similarly, the output resistance of the stage is given by (7.62) Example 7.7 Determine the voltage gain of the circuit shown in Fig. 7.13(a) if .

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 334 (1) 334 Chap. 7 CMOS Amplifiers M 1 V DD M 2 in V out V Figure 7.13 CS stage with diode-connected PMOS device. Solution This stage is similar to that in Fig. 7.12(a), but with NMOS devices changed to PMOS transistors: serves as a common-source device and as a diode-connected load. Thus, (7.63) Exercise Repeat the above example if the gate of is tied to a constant voltage equal to 0.5 V. 7.2.4 CS Stage With Degeneration Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar transistor alters characteristics such as gain, I/O impedances, and linearity. We expect similar results for a degenerated CS amplifier. Figure 7.14 depicts the stage along with its small-signal equivalent (if ). As with the bipolar counterpart, the degeneration resistor sustains a fraction of the input voltage change. From Fig. 7.14(b), we have V R DD M 1 D R S out V in V g m v v 1 1 in v R out v R S D (a) (b) Figure 7.14 (a) CS stage with degeneration, (b) small-signal model. (7.64) and hence (7.65)
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 335 (1) Sec. 7.2 Common-Source Stage 335 Since flows through , and (7.66) (7.67) a result identical to that expressed by (5.157) for the bipolar counterpart. Example 7.8 Compute the voltage gain of the circuit shown in Fig. 7.15(a) if . V R DD M 1 D out V in V (a) (b) M 2 R M 1 D out in v v g 1 m2 Figure 7.15 (a) Example of CS stage with degeneration, (b) simplified circuit. Solution Transistor serves as a diode-connected device, presenting an impedance of [Fig. 7.15(b)]. The gain is therefore given by (7.67) if is replaced with : (7.68) Exercise What happens if for ? In parallel with the developments in Chapter 5, we may study the effect of a resistor appearing in series with the gate (Fig. 7.16). However, since the gate current is zero (at low frequencies), sustains no voltage drop and does not affect the voltage gain or the I/O impedances.

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