Mn4 6 5 0 0 mosn w16u l2u as64p ad64p mp4 6 5 1 1

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MN4 6 5 0 0 MOSN W=16U L=2U AS=64P AD=64P MP4 6 5 1 1 MOSP W=40U L=2U AS=160P AD=160P * MN5 7 6 0 0 MOSN W=16U L=2U AS=64P AD=64P MP5 7 6 1 1 MOSP W=40U L=2U AS=160P AD=160P .OP .TRAN 0.025N 20N .MODEL MOSN NMOS KP=5E-5 VTO=0.91 GAMMA=0.99 +LAMBDA=.02 TOX=41.5N +CGSO=330P CGDO=330P CJ=3.9E-4 CJSW=510P .MODEL MOSP PMOS KP=2E-5 VTO=-0.77 GAMMA=0.5 +LAMBDA=.05 TOX=41.5N +CGSO=315P CGDO=315P CJ=2.0E-4 CJSW=180P .PROBE V(2) V(3) V(5) V(6) .END First inverter : t r = 0.35 ns , t f = 0.35 ns , t PLH = 0.15 ns , t PHL = 0.20 ns Fourth inverter : t r = 0.50 ns , t f = 0.45 ns , t PLH = 0.25 ns , t PHL = 0.30 ns t PHL = R onn C ln 4 V H - V TN V H + V L - 1 + 2 V TN V H - V TN = R onn C ln 4 5 - 1 5 + 0  - 1 + 2 5 - 1 = 1.29 R onn C C 1 = t PHL 1.29 R onn = 2 x 10 - 10 1.29 8 1 50 x 10 - 6 ( 29 5 - 0.91 ( 29 = 254 fF | The inverter is symmetrical, so C 2 = t PLH 1.29 R onp = 1.5 x 10 - 10 1.29 20 1 20 x 10 - 6 ( 29 5 - 0.77 ( 29 = 197 fF | C = 254 + 197 2 fF = 226 fF The average capacitance of 224 fF that is required to fit the results is consistent with the device capacitances calculated by SPICE in the .OP statement. The approximate 2:1 relationship holds between rise/fall times and the propagation delay times. The first inverter response is faster than that of the fourth inverter because of the rapid rise and fall times on the input signal. The first inverter response is closest to our model used for hand calculations. However, the response of inverter four is more representative of the actual logic situation. 7.31 ( a ) 2 W 10 6 gates = 2 m W / gate ; P = CV DD 2 f ; C = 2 x 10 -6 5 2 5 x 10 6 ( 29 = 16.0 fF ( b ) C = 2 x 10 -6 3.3 2 5 x 10 6 ( 29 = 36.7 fF 7.32 ( a ) 20 W 5 x 10 6 gates = 4 m W / gate (b) I = 20 W 3.3 V = 6.06 A 7.33
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7-224 a ( 29 I = I S A = 400 pA cm 2 1 cm x 0.5 cm ( 29 = 200 pA b ( 29 I = I S A + 75 x 10 6 ( 29 150 pA cm 2 2.5 x 10 - 4 cm ( 29 1 x 10 - 4 cm ( 29 = 200 + 281 = 481 pA c ( 29 Same as b ( 29 7.34 ( a ) P = 64 CV DD 2 f = 64 25 x 10 -12 ( 29 5 2 ( 29 1 10 - 8 = 4 W | ( b ) P = 64 25 x 10 -12 ( 29 3.3 2 ( 29 1 10 - 8 = 1.74 W 7.35 Assume both transistors are saturated since v O = v I . 20 1 25 x 10 - 6 2 v I - V TN ( 29 2 = 20 1 10 x 10 - 6 2 v I - V DD - V TP ( 29 2 1.58 v I - V TN ( 29 = V DD - v I + V TP a ( 29 v O = v I = V DD + 1.58 V TN + V TP 2.58 5 + 1.58 1 ( 29 + - 1 ( 29 2.58 = 2.16 V Peak current occurs for v O = v I : i D = 20 1 25 x 10 - 6 2 2.16 - 1 ( 29 2 = 336 m A Checking the current : i D = 20 1 10 x 10 - 6 2 2.16 - 5 + 1 ( 29 2 = 339 m A | Within roundoff error. b ( 29 v O = v I = 3.3 + 1.58 1 ( 29 + - 1 ( 29 2.58 = 1.504 V | i D = 20 1 25 x 10 - 6 2 1.504 - 1 ( 29 2 = 63.5 m A Checking the current : i D = 20 1 10 x 10 - 6 2 1.504 - 3.3 + 1 ( 29 2 = 63.4 m A | Within roundoff error.
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