To begin, we track the ROC of the graph to determine the location of any poles and zeros.
Since the graph initially has 0 dB/decade ROC, there are no poles or zeros at the origin. The first
change in ROC occurs at
. We know that the ROC will be negative, but we must
confirm the actual value of ROC. To do so, we simply reverse the formula we use to go between
points on the Bode plot:
(
*
(
)
Thus, only a single pole is needed to achieve this ROC:
( )
( )
(
)( )
This ROC continues until
, where there is a zero:
( )
(
)( )
(
)( )
This continues until
, where there is another zero:
( )
(
)(
)
(
)( )
Finally, we have one last pole at
:
( )
(
)(
)
(
)(
)
To match the total gain:
| (
)|
(from graph)
[ (
)(
) (
* (
*]
Thus, we will need a minimum of two op-amps to realize this circuit, or possibly three (if we need
additional pure gain).

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Stage 1
(
)
(
)
Group the nearest pole and zero together
–
we can start with 2000 // 500. We can
try using inductor
/ resistor series networks, as they are simpler to calculate, and we have no particularly low
frequencies.
( )
(
)
We can select
, resulting in:
Now, we need to have some additional gain (
). We could try to reali
ze it here, but let’s try
the simplest case first:
( )
It looks like we may have some room for adjustment here, so let’s try to realize all of the gain, K:
This means we have gone past the minimum value for
. If we instead fix
to the minimum:

61/92
Stage 2
(
)
(
)
Again, we will be using resistor and inductor series networks. This circuit should be easier to
realize, as we even higher frequencies than Stage 1.
( )
(
)
Start by selecting
:
Try to realize the remaining gain:
Thus, the design is complete, with all requirements met.
Notes:
Full marks would be given to any equivalent solution. Points would not be deducted for using
more components than the above (say, using a separate pure gain stage).
The weakest point of this design is the use of
and
, which are exactly
at the limits of reasonable component values.
We could ease
by using an additional op-amp stage to realize more gain.
Easing
would require a different circuit
–
for low frequencies, it might make sense to use a
R/C parallel network circuit for Stage 1, and keep Stage 2 as-is. However, full marks would
be awarded for a complete solution using only R/L or R/C, so long as (i) all poles and zeros are
located correctly, (ii) the total gain is correct, and (iii) no components are selected outside the
range given.

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62/92
Question 28.
To begin, one can notice a small simplification from the given diagram:
That is, the resistor
plays no role in the transfer function. At this point, we could naively try to
solve the above circuit by writing equations at multiple unknown nodes. As labeled above, one could
write:
(1)
(2)
(3)
We assume that both op-amps are operating in a negative feedback mode, such that
for both.
We also replace
with their equivalent values. Note that we cannot write node equations
directly at the nodes
(input to circuit),
, or
(outputs of op-amps).

- Spring '17