Transmit FIFO interrupt condition has not occurred 1 Transmit FIFO interrupt

Transmit fifo interrupt condition has not occurred 1

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Transmit FIFO interrupt condition has not occurred. 1 Transmit FIFO interrupt condition has occurred. 6 TXFFINTCLR Transmit FIFO interrupt flag clear bit. 0 Writes of zeros have no effect. Reads return a 0. 1 Writing a 1 to this bit clears the TXFFINT flag. 5 TXFFIENA Transmit FIFO interrupt enable bit. 0 Disabled. TXFFINT flag does not generate an interrupt when set. 1 Enabled. TXFFINT flag does generate an interrupt when set. 4-0 TXFFIL4-0 Transmit FIFO interrupt level. These bits set the status level that will set the transmit interrupt flag. When the TXFFST4-0 bits reach a value equal to or less than these bits, the TXFFINT flag will be set. This will generate an interrupt if the TXFFIENA bit is set. The I2C receive FIFO register (I2CFFRX) is a 16-bit register that contains the control and status bits for the receive FIFO mode of operation on the I2C peripheral. The bit fields are shown in Figure 31 and described in Table 22 . Figure 31. I2C Receive FIFO Register (I2CFFRX) 15 14 13 12 11 10 9 8 Reserved RXFFRST RXFFST4 RXFFST3 RXFFST2 RXFFST1 RXFFST0 R-0 R/W-0 R-0 R-0 R-0 R-0 R-0 7 6 5 4 3 2 1 0 RXFFINT RXFFINTCLR RXFFIENA RXFFIL4 RXFFIL3 RXFFIL2 RXFFIL1 RXFFIL0 R-0 R/W1C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset SPRUG03A–August 2008–Revised July 2009 TMS320x280x Inter-Integrated Circuit Module 35 Submit Documentation Feedback
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