Module Five

Implemented by the operating system or the hardware

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Implemented by the Operating System or the Hardware. Instruction Execution Cycle Two Phases n Fetch n CPU presents address of the instruction to memory n Retrieves instructions located at that address n Execute n Instruction is decoded and executed n Controlled by the CPU clock signals n Multi-Phase clock signals used for DRAM n Single Phase clock signals used for SRAM n Some instructions require more than one machine cycle to execute n Different States of Operation: n Run or operating state n Application or problem state n Non-privileged instruction – subset of instructions for user n Supervisory State n Privileged instructions – System Administrator may execute n Wait State - accessing slow memory Modern Computer Enhancements n Pipelining – increases performance by overlapping the steps of instructions n Three Phases - Fetch – Decode – Execute n Complex Instruction Set – instructions perform many operations per instruction, based on taking advantage of longer fetch times n Reduced Instruction Set - simpler instruction that require less clock cycles to complete n Result of faster processors that enabled the fetch process to be done as quickly as decode and Execute n Scalar Processor – processor that executes one instruction at a time n Superscalar Processor – processor that enables concurrent execution of multiple instructions in the same pipeline
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n Very Long Instruction Word Processor – VLIW – processor in which a single instruction specifies more than one concurrent operation n Multiprogramming – Executes two or more programs simultaneously on a single processor n Multitasking – Executes two or more subprograms at the same time on a single processor n Multiprocessor – Executes two or more programs at the same time on multiple processors Input / Output Structures n A processor communicates with outside devices through (I/O) interface adapters n Complex provide n Data buffering n Timing and interrupt controls n Adapters have addresses on the computer bus n If the adapter has address in the memory space it is known on memory-mapped (I/O) n Benefit is that CPU sees adapter as any other memory device Types of I/O: n Block devices (write blocks of data; hard disk) n Character devices (not addressable; keyboard and printer) CPU operating states: ready state, problem state, supervisory state, and wait state Direct Memory Access – DMA Data is transferred directly to and from the memory bypassing the CPU Interrupt Processing – an external signal interrupts the normal program flow and requests service, when the service is complete the CPU restores the state of the original program, CPU can turn off interrupts n Software – Binary codes is machine language instructions n Assembly Language - Mnemonics for basic instruction set specific to the computer n One to one relationship for each assembly instruction to each machine instruction n Source code - assembly goes through assembler to become object (machine) code n Disassembler will reverse machine code into assembly
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Implemented by the Operating System or the Hardware...

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