# 779 thus if the circuit is driven by a finite source

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(7.79) Thus, if the circuit is driven by a finite source impedance [Fig. 7.20(b)], the voltage gain falls to (7.80) where is assumed to be zero. As mentioned in Chapter 5, it is possible to utilize degeneration for bias point stability but eliminate its effect on the small-signal performance by means of a bypass capacitor [Fig. 7.20(c)]. Unlike the case of bipolar realization, this does not alter the input impedance of the CS stage: (7.81) but raises the voltage gain: (7.82) Example 7.11 Design the CS stage of Fig. 7.20(c) for a voltage gain of 5, an input impedance of 50 k , and a power budget of 5 mW. Assume , V, , and V. Also, assume a voltage drop of 400 mV across .

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 339 (1) Sec. 7.2 Common-Source Stage 339 Solution The power budget along with V implies a maximum supply current of 2.78 mA. As an initial guess, we allocate 2.7 mA to and the remaining 80 A to and . It follows that (7.83) As with typical design problems, the choice of and is somewhat flexible so long as . However, with known, we must ensure a reasonable value for , e.g., V. This choice yields (7.84) (7.85) and hence (7.86) Writing (7.87) gives (7.88) With V and a 400-mV drop across , the gate voltage reaches 1.4 V, requiring that (7.89) which, along with , yields, (7.90) (7.91) We must now check to verify that indeed operates in saturation. The drain voltage is given by . Since the gate voltage is equal to 1.4 V, the gate-drain voltage difference exceeds , driving into the triode region! How did our design procedure lead to this result? For the given , we have chosen an ex- cessively large , i.e., an excessively small (because ), even though is reasonable. We must therefore increase so as to allow a lower value for . For example, suppose we halve and double by increasing by a factor of four: (7.92) (7.93)
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 340 (1) 340 Chap. 7 CMOS Amplifiers The corresponding gate-source voltage is obtained from (7.84): (7.94) yielding a gate voltage of 650 mV. Is in saturation? The drain voltage is equal to V, a value higher than the gate voltage minus . Thus, operates in saturation. Exercise Repeat the above example for a power budget of 3 mW and V. 7.3 Common-Gate Stage Shown in Fig. 7.21, the CG topology resembles the common-base stage studied in Chapter 5. Here, if the input rises by a small value, , then the gate-source voltage of decreases by the same amount, thereby lowering the drain current by and raising by . That is, the voltage gain is positive and equal to V R DD D out V M 1 V b in V Input Applied to Source Output Sensed at Drain Figure 7.21 Common-gate stage. (7.95) The CG stage suffers from voltage headroom-gain trade-offs similar to those of the CB topol- ogy. In particular, to achieve a high gain, a high or is necessary, but the drain voltage, , must remain above to ensure is saturated.

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